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    An integrated circuit with automatic compensation for deviations of the capacitances from nominal values
    5.
    发明公开
    An integrated circuit with automatic compensation for deviations of the capacitances from nominal values 失效
    有能力的期望值的偏差的自动补偿集成电路

    公开(公告)号：EP0794609A1

    公开(公告)日：1997-09-10

    申请号：EP96830103.6

    申请日：1996-03-08

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Demicheli, Marco ,  Pisati, Valerio

    IPC: H03B1/00 ,  H03L7/099

    CPC classification number: H03L7/0805 ,  H03L7/099

    Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors.
    In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

    Abstract translation: 所描述的系统包括各种电路单元（10，11，12），每个具有一个电容器（C0，C1，C2）和用于在所述之间的比率（I / C）定义的量DEPENDING充电装置（G0，G1，G2） 充电电流和电容器的电容。 为了由于在集成电路制造工艺的参数的波动自动为从标称电容的实际电容的偏差进行补偿，该系统具有电路单元的锁相环（PLL），其使用（10）之一 作为可调振荡器，和电流传感器装置（17）从而调节电容器的电路单元的充电电流（C1，C2）（11，12）在根据所述振荡器的电容器的调节充电电流（C0） （10）或者PLL环路的误差电流。

    Method for reducing the settling time in PLL circuits
    7.
    发明公开
    Method for reducing the settling time in PLL circuits 有权
    Verfahren zur Reduzierung der Einschwingzeit von PLL Schaltungen

    公开(公告)号：EP0993122A1

    公开(公告)日：2000-04-12

    申请号：EP98830586.8

    申请日：1998-10-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Filoramo, Pietro ,  Cosentino, Gaetano

    IPC: H03L7/10 ,  H03L7/189 ,  H03J5/02

    CPC classification number: H03L7/189

    Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, which comprise a phase comparator (2), a filter (4), a digital-analog converter (8) and an adder (5) which are suitable to produce in output a voltage (V c ) for controlling a voltage-controlled oscillator (6) provided by means of a varactor, characterized in that it comprises the steps of:

    -- determining the dependency of the control voltage (V c ) of the voltage-controlled oscillator (6) on the frequency of a selected channel of a transmitter;
    -- generating a law describing the variation of the output current (I DAC ) of said digital-analog converter (8) such that the voltage (V DAC ) obtained from the output current of the digital-analog converter, added to an output voltage (V f ) of said filter (4), is such as to keep said filter voltage (V f ) constant, in order to reduce the settling time of the PLL circuit as a selected channel varies.

    Abstract translation: 一种用于减少PLL电路中的建立时间的方法，特别是用于RF收发器中的方法，其包括相位比较器（2），滤波器（4），数模转换器（8）和加法器（5） 适于在输出中产生用于控制由变容二极管提供的压控振荡器（6）的电压（Vc），其特征在于包括以下步骤：确定电压 - 电压的控制电压（Vc） 控制振荡器（6）在发射机的选定信道的频率上; 产生描述所述数模转换器（8）的输出电流（IDAC）的变化的定律，使得从数模转换器的输出电流获得的电压（VDAC）加到输出电压（Vf）上 所述滤波器（4）为了保持所述滤波器电压（Vf）恒定，以便随着所选择的信道变化而减小PLL电路的建立时间。

    BICMOS transconductor differential stage for high-frequency filters
    9.
    发明公开
    BICMOS transconductor differential stage for high-frequency filters 失效
    用于高频滤波器的BICMOS跨导差分级

    公开(公告)号：EP0810723A1

    公开(公告)日：1997-12-03

    申请号：EP96830311.5

    申请日：1996-05-31

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME.

    Inventor： Pisati, Valerio ,  Alini, Roberto ,  Cosentino, Gaetano ,  Vai, Gianfranco

    IPC: H03H1/00 ,  H03F3/45 ,  H03F3/72

    CPC classification number: H03F3/72 ,  H03F3/45286 ,  H03F2203/45302 ,  H03F2203/45304 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45506

    Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2).
    In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

    Abstract translation: 一种用于高频滤波器的BiCMOS跨导差分级（10）包括具有信号输入端（IN +，IN-）并包括一对MOS晶体管（M1，M2）的输入电路部分，所述一对MOS晶体管的各自的栅极端子（G1，G2） 信号输入端以及具有信号输出端（OUT-，OUT +）的输出电路部分，并且包括在电路节点（B）中用公共基极连接在一起的一对双极晶体管（Q1，Q2），并插入在输入端 （IN +，IN-）和输出（OUT-，OUT +）级联配置。 根据本发明的级（10）需要与所述增加的双极晶体管（Q1，Q2）中的至少一个相关联的开关器件（3）改变跨导级中存在的寄生电容器之间的连接。 开关器件（3）还包括至少一个与对应的双极共源共栅晶体管（Q1，Q2）并联连接的增加的双极晶体管（Q1x，Q2x）。 在变型实施例中，还提供了与输入部分的MOS晶体管（M1，M2）并联连接的相应增加的MOS晶体管（M1x，M2x），以改变每个输入晶体管（M1，M2）的比率W:L ）。

    An amplifier with a low offset
    10.
    发明公开
    An amplifier with a low offset 失效
    EinVerstärkermit Niedrigem Offset

    公开(公告)号：EP0786858A1

    公开(公告)日：1997-07-30

    申请号：EP96830035.0

    申请日：1996-01-26

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Alini, Roberto ,  Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Pisati, Valerio

    IPC: H03F1/00 ,  H03F3/30

    CPC classification number: H03F3/3077

    Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage.
    The amplifier has a very low or zero offset ( Vos = Vout-Vin ).

    Abstract translation: 所描述的放大器具有由推挽装置中的npn晶体管（Q1）和pnp晶体管（Q2）和驱动器级构成的输出级。 后者包括电流镜电路，其在其输入支路中具有与第一恒定电流发生器（G1）串联的pnp晶体管（Q3），并且在其输出支路中具有npn晶体管（Q4）和两个互补的 集电极一起连接到输出端（OUT）的晶体管（Q5和Q6）和基极连接在放大器的输入端（IN）上。 驱动级的pnp晶体管（Q5）的发射极通过第二恒流发生器（G2）连接到电源的正端子（vdd），并连接到电源的npn晶体管（Q1）的基极 输出级，并且驱动级的npn晶体管（Q6）的发射极通过电流镜电路的输出支路的npn晶体管（Q4）连接到电源的负极（gnd），并且 输出级的pnp晶体管（Q2）的基极。 放大器具有非常低或零偏移（Vos = Vout-Vin）。

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