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    BICMOS transconductor differential stage for high-frequency filters
    2.
    发明公开
    BICMOS transconductor differential stage for high-frequency filters 失效
    用于高频滤波器的BICMOS跨导差分级

    公开(公告)号：EP0810723A1

    公开(公告)日：1997-12-03

    申请号：EP96830311.5

    申请日：1996-05-31

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME.

    Inventor： Pisati, Valerio ,  Alini, Roberto ,  Cosentino, Gaetano ,  Vai, Gianfranco

    IPC: H03H1/00 ,  H03F3/45 ,  H03F3/72

    CPC classification number: H03F3/72 ,  H03F3/45286 ,  H03F2203/45302 ,  H03F2203/45304 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45506

    Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2).
    In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

    Abstract translation: 一种用于高频滤波器的BiCMOS跨导差分级（10）包括具有信号输入端（IN +，IN-）并包括一对MOS晶体管（M1，M2）的输入电路部分，所述一对MOS晶体管的各自的栅极端子（G1，G2） 信号输入端以及具有信号输出端（OUT-，OUT +）的输出电路部分，并且包括在电路节点（B）中用公共基极连接在一起的一对双极晶体管（Q1，Q2），并插入在输入端 （IN +，IN-）和输出（OUT-，OUT +）级联配置。 根据本发明的级（10）需要与所述增加的双极晶体管（Q1，Q2）中的至少一个相关联的开关器件（3）改变跨导级中存在的寄生电容器之间的连接。 开关器件（3）还包括至少一个与对应的双极共源共栅晶体管（Q1，Q2）并联连接的增加的双极晶体管（Q1x，Q2x）。 在变型实施例中，还提供了与输入部分的MOS晶体管（M1，M2）并联连接的相应增加的MOS晶体管（M1x，M2x），以改变每个输入晶体管（M1，M2）的比率W:L ）。

    Integrated circuit with identification signal writing circuitry distributed on multiple metal layers
    4.
    发明公开
    Integrated circuit with identification signal writing circuitry distributed on multiple metal layers 审中-公开
    包括：在多个金属层的集成电路分布式布线用于写入的识别信号

    公开(公告)号：EP1100125A1

    公开(公告)日：2001-05-16

    申请号：EP99830699.7

    申请日：1999-11-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vai, Gianfranco ,  Savo, Pierandrea

    IPC: H01L23/544 ,  G06F11/00 ,  G11C17/10

    CPC classification number: G11C17/10 ,  G06F11/006 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated device (100) comprising a plurality of conducting layers (115a-115c), each having a first (120ga-120gc) and a second (120va-120vc) power supply contact for providing, respectively, a first and a second binary value, and means for supplying at least one identification bit of a version of the integrated device (100); the integrated device (100) includes, for each identification bit, parity check means (135abi, 135bci) having a plurality of input terminals whose number is equal to the number of conducting layers (115a-115c), and an output terminal, each input terminal being connected to one contact selected from the first (120ga-120gc) and the second (120va-120vc) power supply contacts of a corresponding one of the conducting layers (115a-115c), and the output terminal supplying the corresponding identification bit.

    Abstract translation: 集成器件（100）包括导电层（115A-115C）的复数，每个都具有第一（120ga-120gc）和用于提供第二（120VA-120vc）供电接触件，分别为第一和第二二进制值， 和装置，用于提供一个版本的集成设备（100）中的至少一个识别位; 集成器件（100）包括，对于每个识别位，奇偶校验手段（135abi，135bci），其具有输入端子，其数量等于导电层（115A-115C）的数量，和输出端子的复数，每个输入 端子被连接到从第一（120ga-120gc）选择的一个接触，并且相应的所述导电层中的一个（115A-115C）的第二个（120VA-120vc）电源触点，和输出端供给对应的识别位。

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