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    Integrated resistive element, phase-change memory element including said resistive element, and method of manufacture thereof
    1.
    发明公开
    Integrated resistive element, phase-change memory element including said resistive element, and method of manufacture thereof 有权
    集成电阻元件，其具有用于其制备这样的电阻元件和过程的相变存储器元件

    公开(公告)号：EP1331675A1

    公开(公告)日：2003-07-30

    申请号：EP02425013.6

    申请日：2002-01-17

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Zonca, Romina ,  Marangon, Maria Santina ,  De Santi, Giorgio

    IPC: H01L45/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: A vertical-current-flow resistive element (12) comprising a monolithic region (12) having a first portion (12a) and a second portion (12b) arranged on top of one another and formed by a single material. The first portion has a first resistivity, and the second portion (12b) has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion (12a) is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion (12a) than in the second portion (12b). Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi 2 , Ta, WSi, and the increase in resistivity is obtained by nitridation.

    Abstract translation: 的垂直电流流电阻元件（12）包括具有第一部分（12a）和（12b）的布置在彼此的顶部上，并通过一个单一的材料形成的第二部分的单片区域（12）。 所述第一部分具有第一电阻率，并且所述第二部分（12b）具有第二电阻率，比所述第一电阻率。 为了这个目的，具有均匀的电阻率和高度比其他尺寸首先形成的至少一个大的整体区域; 然后所述第一部分（12a）的电阻率是通过引入，从顶部增加，物种确实形成具有单片区域的导电材料的普遍地共价键，所以没有所述物质的浓度变得在第一部分更高（12A ）比（在第二部分12b）。 优选地，导电材料是二元或三元合金，从TiAl金属，的TiSi2，钽，的WSi选自，和电阻率的增加是由氮化获得。

    Manufacturing method of an integrated circuit formed on a semiconductor substrate
    5.
    发明公开
    Manufacturing method of an integrated circuit formed on a semiconductor substrate 审中-公开
    一种制造集成电路的过程中在半导体衬底上

    公开(公告)号：EP1895578A1

    公开(公告)日：2008-03-05

    申请号：EP06425606.8

    申请日：2006-09-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bresolin, Camillo ,  Erbetta, Davide ,  Marangon, Maria Santina

    IPC: H01L21/311 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L21/31111 ,  H01L21/31144 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531

    Abstract: Method for manufacturing an integrated circuit (101; 102; 1) formed on a semiconductor substrate (201; 2) comprising the steps of:
    - forming at least one shielding structure (60; 61; 6A, 6B) on said semiconductor substrate (201; 2),
    - forming a protective layer (100, 190; 19, 11') at least on portions of the semiconductor substrate (201; 2) that surround said shielding structure (60; 6A, 6B),
    - carrying out a ionic implantation step with a tilt angle with respect to a normal to a plane defined by said semiconductor substrate (201; 2) so that said at least one shielding structure (60; 61; 6A, 6B) shields first portions (200; 202; 20, 11A) of the protective layer (100, 190; 19, 11'),
    - removing second portions (210; 211; 21, 11B) of the protective layer (100, 190; 19, 11') that have been subjected to the ionic implant.

    Abstract translation: 用于制造集成电路的方法（101; 102; 1）形成在半导体衬底上（201; 2）包括以下步骤： - 形成至少一个屏蔽结构（60; 61; 6A，6B）在所述半导体衬底（201 ; 2）， - 形成保护层（100，190;在半导体衬底（201的部分的至少19，11“），2）没有环绕所述屏蔽结构（60; 6A，6B）， - 执行一个离子 有倾斜角度相对于一个垂直于由所述半导体衬底限定的平面注入步骤（201，2），使得所述至少一个屏蔽结构（60; 61; 6A，6B）屏蔽的第一部分（200; 202; 20 中，保护层（100的11A），190; 19，11 '）， - 去除第二部分（210;保护层（100，190的21，图11B）; 211 19，11'）并已经经受 离子植入。

    Process for manufacturing a memory with local electrical contact between the source line and the well
    6.
    发明公开
    Process for manufacturing a memory with local electrical contact between the source line and the well 审中-公开
    一种用于制造存储器与所述源极线和所述阱之间的局部电接触方法

    公开(公告)号：EP1686620A1

    公开(公告)日：2006-08-02

    申请号：EP05425034.5

    申请日：2005-01-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Brazzelli, Daniela ,  Servalli, Giorgio ,  Erbetta, Davide ,  Marangon, Maria Santina

    IPC: H01L21/768 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/115 ,  H01L27/11521

    Abstract: In a process for manufacturing a memory (2) having a plurality of memory cells (3) the steps of: forming a well (11), having a first type of conductivity, within a wafer (10) of semiconductor material; defining active regions (12) within the well (11) extending in a first direction (y); forming memory cells (3) within the active regions (12), each memory cell (3) having a source region (15) with a second type of conductivity, opposite to the first type of conductivity; and forming lines of electrical contact (20), which electrically contact source regions (15) aligned in a second direction (x). In the step of forming lines of electrical contact (20), the step of forming an electrical contact between the source regions (15) and portions (37) of the well (11) adjacent thereto in the second direction (x).

    Abstract translation: 在用于制造具有存储器单元（3）的步骤的多个A存储器（2）的方法：形成阱（11），具有第一导电类型的半导体材料的晶片（10）内; 在第一方向（Y）延伸的孔（11）内 - 定义的有源区（12）; 有源区域内形成存储单元（3）（12），每个存储单元（3）具有与第二导电类型的，相反于第一导电类型的源极区（15）; 和在第二方向上排列的电接触件（20），该电接触源极区（15）的成型线（X）。 在形成电接触（20），在第二方向（x）的阱（11）与其相邻的源极区（15）和部分（37）之间的电接触形成的步骤的线的步骤。

    Dual resistance heater for phase change devices and manufacturing method thereof
    7.
    发明公开
    Dual resistance heater for phase change devices and manufacturing method thereof 审中-公开
    Zweiteiliger WiderstandsheiserfürPhasenwechselspeicher und Herstellungsmethode

    公开(公告)号：EP1677371A1

    公开(公告)日：2006-07-05

    申请号：EP04107070.7

    申请日：2004-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Kim, Yudong ,  Karpov, Ilya V. ,  Kuo, Charles C. ,  Atwood, Greg ,  Marangon, Maria Santina ,  Lowrey, Tyler

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/1683

    Abstract: A dual resistance heater (24) for a phase change material region (28) is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface (26) of the heater material relative to the remainder (27) of the heater material. As a result, the portion (26) of the heater material approximate to the phase change material region (28) is a highly effective heater because of its high resistance, but the bulk (27) of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

    Abstract translation: 通过沉积电阻材料形成用于相变材料区域（28）的双电阻加热器（24）。 然后将加热器材料暴露于植入或等离子体，这增加了加热器材料的表面（26）相对于加热器材料的剩余部分（27）的电阻。 结果，加热器材料的部分（26）由于其高电阻而接近于相变材料区域（28）是高效的加热器，但是加热器材料的体积（27）不是电阻的， 因此，不会增加设备的电压降和当前的使用。

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