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    Sensing circuit with regulated reference voltage
    1.
    发明公开
    Sensing circuit with regulated reference voltage 有权
    Abfühlschaltungmit regulierter Referenzsponung

    公开(公告)号：EP1566809A1

    公开(公告)日：2005-08-24

    申请号：EP04290449.0

    申请日：2004-02-19

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics S.A.

    Inventor： Demange, Nicolas ,  Conte, Antonino ,  Preciso, Salvatore ,  Signorello, Alfredo

    IPC: G11C7/14 ,  G11C7/10

    CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C16/28

    Abstract: A sensing circuit (120) for sensing currents, including at least one sense amplifier (122), comprising: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V-); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and means (N3s,135; N3s,135';N3s,135" ) for generating the comparison current based on a reference current (Ir), said means comprising: at least one voltage generator (135;135';135'') for receiving the reference current and for generating a corresponding sense amplifier biasing voltage (Vsab); and means (N3s) for converting the sense amplifier biasing voltage into the comparison current. The at least one voltage generator includes a first circuit branch (232i), having a first node for receiving the reference current, for converting the reference current into a corresponding reference voltage (Vref), a second circuit branch (232o), having a second node for receiving a regulation current (Ii), in current mirror configuration with the first circuit branch for mirroring a current (Img) corresponding to the reference current, the second circuit branch generating by conversion a non-regulated voltage (Vgen) corresponding to the mirrored current and to the regulation current, and voltage regulator means (N3g,240) receiving the reference voltage and the non-regulated voltage for regulating the sense amplifier biasing voltage by controlling the non-regulated voltage through the regulation current.

    Abstract translation: 一种用于感测电流的感测电路（120），包括至少一个读出放大器（122），包括：测量电路分支（132i），具有用于接收待感测的输入电流（Ic）的测量节点，用于转换输入 电流进入相应的输入电压（V-）; 至少一个比较电路分支（132o），具有用于接收比较电流（Igs）的比较节点，用于将比较电流转换成对应的比较电压（V +）; 和用于比较输入和比较电压的至少一个电压比较器（140）和用于基于参考电流（Ir）产生比较电流的装置（N3s，135; N3s，135'; N3s，135“）， 包括：用于接收所述参考电流并用于产生相应的读出放大器偏置电压（Vsab）的至少一个电压发生器（135; 135'; 135“）;以及用于将所述读出放大器偏置电压转换成比较的装置（N3s） 所述至少一个电压发生器包括第一电路分支（232i），其具有用于接收所述参考电流的第一节点，用于将所述参考电流转换为对应的参考电压（Vref）;第二电路分支（232o），具有 用于以电流镜配置接收调节电流（Ii）的第二节点，其中第一电路支路用于镜像对应于参考电流的电流（Img），第二电路支路通过转换产生非调节电压（ Vgen）和调节电流相对应的电压调节器装置（N3g，240）以及通过调节电流控制非调节电压来调节读出放大器偏置电压的非调节电压 。

    Level-shifter circuit
    3.
    发明公开
    Level-shifter circuit 有权
    PEGELUMSETZER

    公开(公告)号：EP2506432A1

    公开(公告)日：2012-10-03

    申请号：EP12162761.6

    申请日：2012-03-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ucciadello, Carmelo ,  Conte, Antonino ,  Signorello, Alfredo

    IPC: H03K3/356 ,  H03K17/10

    CPC classification number: H03K17/102 ,  H03K3/356113

    Abstract: A level-shifter circuit (10) has: a pair of inputs which receive a first and a second low-voltage phase signal (FX, FN), having a first voltage dynamics with a first maximum value (Vdd); and a pair of outputs which supply a first high-voltage phase signal (FHX) and a second high-voltage phase signal (FHN), level-shifted with respect to the low-voltage signals and having a second voltage dynamics with a second maximum value (VddH), higher than the first maximum value (Vdd); the circuit is further provided with transfer transistors (M n1 , M n2 , M p1 , M p2 ) coupled between a first reference terminal or a second reference terminal, which are set at a first reference voltage (Gnd) or a second reference voltage (VddH), and the first output or second output; and protection elements (M nc1 , M nc2 , M pc1 , M pc2 ) coupled to a respective transfer transistor in such a way as to protect it from overvoltages between the corresponding conduction terminals and/or control terminals.

    Abstract translation: 电平移位器电路（10）具有：一对输入，其接收具有第一最大值（Vdd）的第一电压动态特性的第一和第二低电压相位信号（FX，FN）; 以及一对输出，其提供相对于所述低电压信号电平移位的第一高电压相位信号（FHX​​）和第二高电压相位信号（FHN），并且具有第二电压动态特性，具有第二最大值 值（VddH），高于第一最大值（Vdd）; 电路还设置有耦合在第一参考端子或第二参考端子之间的转换晶体管（M n1，M n2，M p1，M p2），其被设置在第一参考电压（Gnd）或第二参考电压 VddH）和第一输出或第二输出; 以及耦合到各个传输晶体管的保护元件（M nc1，M nc2，M pc1，M pc2），以保护其免受相应的导通端子和/或控制端子之间的过电压。

    Electrically word-erasable non-volatile memory-device, and biasing method thereof
    4.
    发明公开
    Electrically word-erasable non-volatile memory-device, and biasing method thereof 审中-公开
    Elektrisch wort-löschbarenicht-flüchtigeSpeicheranordnung unddazugehörigesVorspannungsverfahren

    公开(公告)号：EP1569242A1

    公开(公告)日：2005-08-31

    申请号：EP04425123.9

    申请日：2004-02-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Conte, Antonino ,  Micciche, Mario ,  Di Martino, Alberto José ,  Signorello, Alfredo

    IPC: G11C16/16 ,  G11C16/24 ,  G11C16/34

    CPC classification number: G11C16/24 ,  G11C16/16 ,  G11C16/34

    Abstract: A memory device (10) formed by an array of memory cells (13) extending in rows and columns. The device is formed by a plurality of N-type wells (2) extending parallel to the rows; each N-type well (2) houses a plurality of P-type wells (3) extending in a direction transverse to the rows. A plurality of main bitlines (MBL) extend along the columns. Each P-type well is associated to a set of local bitlines (LBL) that extend along the respective P-type well and are connected to the drain terminals (D) of the cells accommodated in the respective P-type well. Local-bitlines managing circuits (14) are provided for each P-type well (3) and are arranged between the main bitlines (MBL) and a respective set of local bitlines (LBL) for controllably connecting each local bitline to a respective main bitline.

    Abstract translation: 一种由行和列延伸的存储单元阵列形成的存储器件（10）。 该装置由平行于行延伸的多个N型阱（2）形成; 每个N型井（2）容纳在横向于行的方向上延伸的多个P型井（3）。 多个主位线（MBL）沿列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线（LBL）相关联，并连接到容纳在相应P型阱中的单元的漏极端子（D）。 为每个P型阱（3）提供局部位线管理电路（14），并且布置在主位线（MBL）和相应的一组本地位线（LBL）之间，用于将每个本地位线可控地连接到相应的主位线 。

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