公开(公告)号：EP1727153A1

公开(公告)日：2006-11-29

申请号：EP05104465.9

申请日：2005-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Sberno, Giampiero ,  Micciche', Mario ,  Castaldo, Enrico

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A non-volatile memory device is proposed. The memory device (100) includes a plurality of blocks (115) of memory cells (125), each block having a common biasing node (SL) for all the memory cells of the block, biasing means (150) for providing a biasing voltage, and selection means (140, 145) for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means (N8, N9, N10) and second switching means (N7) connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means (145) for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.

Abstract translation: 提出了一种非易失性存储器件。 存储器件（100）包括存储器单元（125）的多个块（115），每个块具有用于块的所有存储单元的公共偏置节点（SL），偏置装置（150）用于提供偏置电压 以及用于选择性地将偏置电压施加到所选块的偏置节点的选择装置（140,145），对于每个块，选择装置包括第一开关装置（N8，N9，N10）和第二开关装置（N7） 所述第一开关装置与所述偏置节点连接，所述第二开关装置与所述偏置装置连接，其中所述块的所述第二开关装置并联连接，所述选择装置包括用于闭合所述第一开关装置的装置， 所有块的切换装置和所有块的第二切换装置，并且用于打开每个未选择块的第二切换装置。

公开(公告)号：EP1727153B1

公开(公告)日：2008-10-15

申请号：EP05104465.9

申请日：2005-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Sberno, Giampiero ,  Micciche', Mario ,  Castaldo, Enrico

IPC: G11C16/16

CPC classification number: G11C16/16

公开(公告)号：EP1304701A1

公开(公告)日：2003-04-23

申请号：EP01830656.3

申请日：2001-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Demange, Nicolas ,  Torrisi, Salvatore ,  Sberno, Giampiero

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A circuit for sensing a ferroelectric non-volatile information storage unit (103,403) comprises a pre-charge circuit (113;413t,413c) for applying a prescribed pre-charge voltage (Vprch) to a storage capacitor (C;Ct,Cc) of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the storage capacitor, depending on an initial polarization state of the storage capacitor. A charge integration circuit (115,CAP;115t,115c,CAPt,CAPc) is provided for integrating an electric charge proportional to the variation in polarization charge experienced by the storage capacitor. The charge integration circuit thus provides an output voltage (Voutsw,Voutln) depending on the polarization state of the storage capacitor. The charge integration circuit may comprises an integration capacitor (CAP;CAPt,CAPc) and current mirror circuit (115;415t,415c) , with a first mirror branch (115a) coupled to the pre-charge circuit and a second mirror branch (115b) coupled to the integration capacitor, for mirroring into the second mirror branch an electric charge (Qsw,Qln) supplied to the information storage unit to compensate for the variation in the polarization charge experienced by the storage capacitor.

Abstract translation: 用于感测铁电非易失性信息存储单元（103,403）的电路包括用于将规定的预充电电压（Vprch）施加到存储电容器（C; Ct，Cc）的预充电电路（113; 413t，413c） 的信息存储单元。 根据存储电容器的初始极化状态，预充电电压导致存储电容器的极化电荷的变化。 提供电荷积分电路（115，CAP; 115t，115c，CAPt，CAPc）用于积分与存储电容器经历的极化电荷的变化成比例的电荷。 因此，电荷积分电路根据存储电容器的极化状态提供输出电压（Voutsw，Voutln）。 电荷积分电路可以包括积分电容器（CAP; CAPt，CAPc）和电流镜电路（115; 415t，415c），其中耦合到预充电电路的第一反射镜分支（115a）和第二反射镜分支（115b ）耦合到积分电容器，用于将提供给信息存储单元的电荷（Qsw，Qln）镜像到第二镜像分支中，以补偿存储电容器经历的极化电荷的变化。