公开(公告)号：EP4160350A1

公开(公告)日：2023-04-05

申请号：EP22192568.8

申请日：2022-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： CIGNOLI, Marco ,  ERRICO, Nicola ,  VILMERCATI, Paolo ,  CASTORINA, Stefano ,  FERRARA, Enrico

IPC: G05F1/56 ,  H03K19/007

Abstract: Disclosed herein is a single integrated circuit chip with a main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic (11) within the chip is a safety area (12') that operates to verify proper operation of the main logic. The safety area (12') is internally powered by an internal regulated voltage (VREG) generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage (PWR_IN) while protecting against shorts of the external line delivering the external voltage. The safety area (12') includes protection circuits (25) that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits (25) serving to protect against shorts of the external line delivering the external analog signals.

公开(公告)号：EP3926348A1

公开(公告)日：2021-12-22

申请号：EP21178626.4

申请日：2021-06-09

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ERRICO, Nicola ,  VILMERCATI, Paolo ,  CIGNOLI, Marco ,  GENNA, Vincenzo Salvatore ,  ALAGNA, Diego

IPC: G01R19/00 ,  G01R19/165 ,  H02M1/00

Abstract: A circuit (100') comprises a high-side switch (HS) and a low-side switch (LS) arranged between a supply node (D) and a reference node (G), the high-side and low-side switches having an intermediate node (Q). A switching control signal ( com ) is applied with opposite polarities to the high-side and low-side switches. An inductive load (L) is coupled between the intermediate node (Q) and one of said supply node (D) and said reference node (G).
The circuit (100') further comprises current sensing circuitry (CS') configured to:
sample (12a, 14a) a first value ( I a ) of the load current flowing in one of the high-side and low-side switches at a first sampling instant ( t 1 ) before a commutation ( t s ) of the switching control signal ( com ),
sample (12b, 14b) a second value ( I b ) of the load current flowing in the other of the high-side and low-side switches at a second sampling instant ( t 2 ) after said commutation ( t s ) of said switching control signal ( com ),
sample (12b, 14c) a third value ( I c ) of the load current flowing in the other of the high-side and low-side switches at a third sampling instant ( t 3 ) after said second sampling instant ( t 2 ), and
generate (18) a failure signal ( fail ) as a function of said first ( I a ), second ( I b ) and third ( I c ) sampled values of the load current.