公开(公告)号：EP3648349A1

公开(公告)日：2020-05-06

申请号：EP19203837.0

申请日：2019-10-17

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ALAGNA, Diego ,  ERRICO, Nicola ,  CIGNOLI, Marco ,  DE AGOSTINI, Gian Battista

IPC: H03K7/08 ,  H02M3/157

Abstract: A PWM signal generator (12) configured (D) to provide a supply current (I LOAD ) to an electrical load (L) generates PWM signals at a first frequency (f PWM ), the PWM signals having a duty cycle.
Operating the generator involves:
- receiving a set point signal (SP) indicative of a target average value for the supply current (I LOAD ),
- sensing (20) a sensing signal indicative of a current actual value of the supply current (I LOAD ),
- performing a closed-loop control of the supply current (I LOAD ) targeting the target value (SP) for the supply current via a controller (14; 141, 142, 143, 144) such as a PID Controller which controls (PID) the duty cycle of the PWM signals generated by the PWM signal generator (12) as a function of the offset (18) of the sensing signal with respect to the set point signal (SP).

公开(公告)号：EP4160350A1

公开(公告)日：2023-04-05

申请号：EP22192568.8

申请日：2022-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： CIGNOLI, Marco ,  ERRICO, Nicola ,  VILMERCATI, Paolo ,  CASTORINA, Stefano ,  FERRARA, Enrico

IPC: G05F1/56 ,  H03K19/007

Abstract: Disclosed herein is a single integrated circuit chip with a main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic (11) within the chip is a safety area (12') that operates to verify proper operation of the main logic. The safety area (12') is internally powered by an internal regulated voltage (VREG) generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage (PWR_IN) while protecting against shorts of the external line delivering the external voltage. The safety area (12') includes protection circuits (25) that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits (25) serving to protect against shorts of the external line delivering the external analog signals.

公开(公告)号：EP4170906A1

公开(公告)日：2023-04-26

申请号：EP22199382.7

申请日：2022-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： CIGNOLI, Marco ,  POLETTO, Vanni

IPC: H03K17/14 ,  G01R19/00 ,  H03K17/18

Abstract: A circuit, comprising at least one switching transistor (Q LS , Q HS ) having a control terminal configured to receive a control signal (X) as well as a current flow path therethrough, the at least one switching transistor (Q LS , Q HS ) configured to be switched towards a conductive, resp. non-conductive, state in response to the control signal (X) having a first, resp. second, value wherein the current flow path through the at least one switching transistor (Q LS , Q HS ) provides a current flow line (I QLS , I QHS ) between a switching circuit node (VO) and a reference node (VI, PGND), wherein, in the non-conductive state, a voltage drop stress is applied across the at least one switching transistor (Q LS , Q HS ).
The circuit comprises a sense transistor (M LS ) coupled to the least one switching transistor (Q LS , Q HS ) and being a scaled replica thereof, the sense transistor (M LS ) having a current sense flow path therethrough wherein the intensity of the current (I MS ) flowing therein is indicative of the intensity of the current (I QLS , I QHS ) flowing in the current flow path through the at least one switching transistor (Q LS , Q HS ), and coupling circuitry (13, SB, S 1 , S 2 , S 3 , S 4 ) configured to apply the voltage drop stress across the sense transistor (M LS ) in response to the at least one switching transistor (Q LS , Q HS ) being switched towards the non-conductive state, wherein, in response to the at least one switching transistor (Q LS , Q HS ) being switched towards the non-conductive state, the voltage drop stress is replicated across both the at least one switching transistor (Q LS , Q HS ) and across the sense transistor (M LS , M SH ).

公开(公告)号：EP4167484A1

公开(公告)日：2023-04-19

申请号：EP22192903.7

申请日：2022-08-30

Applicant: STMicroelectronics S.r.l.

Inventor： CIGNOLI, Marco

IPC: H03K17/16 ,  H03K17/73

Abstract: An integrated circuit, IC (100) includes: an input terminal; an output terminal; a first reference voltage terminal (131) and a second reference voltage terminal (135); a high-side power switch (127) coupled between the first reference voltage terminal (131) and the output terminal; a low-side power switch (129) coupled between the output terminal and the second reference voltage terminal (135); a first combinational logic (105) and a second combination logic (107) that are coupled to the input terminal; a first driver (111) coupled between the first combinational logic (105) and the high-side power switch; a second driver (113) coupled between the second combinational logic (107) and the low-side power switch; and first comparators (141A/141B) coupled to the second combinational logic (107), where the first comparators are configured to compare a voltage difference between load path terminals of the high-side power switch (127) with a first threshold and a second threshold.

公开(公告)号：EP3926348A1

公开(公告)日：2021-12-22

申请号：EP21178626.4

申请日：2021-06-09

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ERRICO, Nicola ,  VILMERCATI, Paolo ,  CIGNOLI, Marco ,  GENNA, Vincenzo Salvatore ,  ALAGNA, Diego

IPC: G01R19/00 ,  G01R19/165 ,  H02M1/00

Abstract: A circuit (100') comprises a high-side switch (HS) and a low-side switch (LS) arranged between a supply node (D) and a reference node (G), the high-side and low-side switches having an intermediate node (Q). A switching control signal ( com ) is applied with opposite polarities to the high-side and low-side switches. An inductive load (L) is coupled between the intermediate node (Q) and one of said supply node (D) and said reference node (G).
The circuit (100') further comprises current sensing circuitry (CS') configured to:
sample (12a, 14a) a first value ( I a ) of the load current flowing in one of the high-side and low-side switches at a first sampling instant ( t 1 ) before a commutation ( t s ) of the switching control signal ( com ),
sample (12b, 14b) a second value ( I b ) of the load current flowing in the other of the high-side and low-side switches at a second sampling instant ( t 2 ) after said commutation ( t s ) of said switching control signal ( com ),
sample (12b, 14c) a third value ( I c ) of the load current flowing in the other of the high-side and low-side switches at a third sampling instant ( t 3 ) after said second sampling instant ( t 2 ), and
generate (18) a failure signal ( fail ) as a function of said first ( I a ), second ( I b ) and third ( I c ) sampled values of the load current.