公开(公告)号：EP1659636A1

公开(公告)日：2006-05-24

申请号：EP05025285.7

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio, Frisina ,  Ferla, Giuseppe ,  Magri', Angelo ,  Grimaldi, Antonio Giuseppe ,  Bazzano, Gaetano

IPC: H01L29/78 ,  H01L29/49

CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983

Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors (2) and a gate structure (12) comprising a plurality of conductive strips (8) realised with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks (11) connected to a gate pad (30) and at least a connection layer (20) arranged in series to at least one of said conductive strip (8). Such gate structure (12) comprising at least a plurality of independent islands (10) formed on the upper surface (9) of the conductive strips (8) and suitably formed on the connection layers (20). Said islands (10) being realised with at least one second conductive material such as silicide.

Abstract translation: 包括多个基本功率MOS晶体管（2）和栅极结构（12）的功率电子MOS器件包括由诸如多晶硅的第一导电材料实现的多个导电条（8），多个栅极指或者 连接到栅极焊盘（30）的金属轨道（11）和至少与所述导电条（8）中的至少一个串联布置的连接层（20）。 这种栅极结构（12）包括形成在导电条（8）的上表面（9）上并适当地形成在连接层（20）上的至少多个独立的岛（10）。 所述岛（10）用至少一种第二导电材料（例如硅化物）实现。

公开(公告)号：EP1659636B1

公开(公告)日：2009-11-04

申请号：EP05025285.7

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio, Frisina ,  Ferla, Giuseppe ,  Magri', Angelo ,  Grimaldi, Antonio Giuseppe ,  Bazzano, Gaetano

IPC: H01L29/78 ,  H01L29/49

CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983

Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors (2) and a gate structure (12) comprising a plurality of conductive strips (8) realised with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks (11) connected to a gate pad (30) and at least a connection layer (20) arranged in series to at least one of said conductive strip (8). Such gate structure (12) comprising at least a plurality of independent islands (10) formed on the upper surface (9) of the conductive strips (8) and suitably formed on the connection layers (20). Said islands (10) being realised with at least one second conductive material such as silicide.