公开(公告)号：EP4177960A1

公开(公告)日：2023-05-10

申请号：EP22204133.7

申请日：2022-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： CASCINO, Salvatore ,  GUARNERA, Alfio ,  SAGGIO, Mario Giuseppe

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06

Abstract: A semiconductor power device has a maximum nominal voltage and includes: a first conduction terminal (1a) and a second conduction terminal (lb); a semiconductor body (2), containing silicon carbide and having a first conductivity type; body wells (7) having a second conductivity type, housed in the semiconductor body and separated from one another by a body distance (LB); source regions housed in the body wells (7); and floating pockets (20) having the second conductivity type, formed in the semiconductor body (2) at a distance from the body wells (7) between a first face (2a) and a second face (2b) of the semiconductor body (2). The floating pockets (20) are shaped and arranged relative to the body wells (7) so that a maximum intensity of electrical field around the floating pockets (20) is greater than a maximum intensity of electrical field around the body wells (7) at least for values of an operating voltage (VDS) between the first conduction terminal (1a) and the second conduction terminal (1b) greater than a threshold voltage, the threshold voltage being less than the maximum nominal voltage.

公开(公告)号：EP4047664A1

公开(公告)日：2022-08-24

申请号：EP22155166.6

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio ,  CAMALLERI, Cateno Marco

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/336

Abstract: A vertical-conduction MOSFET device (50) formed in a body (55) of silicon carbide having a first and a second face (52A, 52B) and a peripheral zone (87). A drain region (57), of a first conductivity type, extends in the body (55) between the two faces. A body region (60), of a second conductivity type, extends in the body from the first face (55A), and a source region (65), having the first conductivity type, extends to the inside of the body region (60) from the first face (55A) of the body. An insulated gate region (70) extends on the first face of the body and comprises a gate conductive region (72). An annular connection region (86), of conductive material, is formed within a surface edge structure extending on the first face (55A) of the body (55), in the peripheral zone (87). The gate conductive region (72) and the annular connection region (86) are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.

公开(公告)号：EP3930007A1

公开(公告)日：2021-12-29

申请号：EP21180931.4

申请日：2021-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  MAGRI', Angelo ,  ZANETTI, Edoardo ,  GUARNERA, Alfio

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36

Abstract: Electronic device (100) comprising: a semiconductor body (102) of silicon carbide; a body region (105) at a first surface of the semiconductor body; a source region (108) in the body region (105); a drain region (104) at a second surface of the semiconductor body (102); a doped region (120) extending seamlessly at the entire first surface (102a) of the semiconductor body (102) and including one or more first sub-regions (121) having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

公开(公告)号：EP4333073A1

公开(公告)日：2024-03-06

申请号：EP23182331.1

申请日：2023-06-29

Applicant: STMicroelectronics S.r.l.

Inventor： FIORENZA, Patrick ,  ROCCAFORTE, Fabrizio ,  ZANETTI, Edoardo ,  SAGGIO, Mario Giuseppe

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/872 ,  H01L21/336 ,  H01L29/12

Abstract: Electronic device (20; 60) comprising: a semiconductor body (48; 68), in particular of Silicon Carbide, SiC, having a first (48a; 68a) and a second face (48b; 68b), opposite to each other along a first direction (Z); and an electrical terminal (G; 82, 74) at the first face (48b; 68b), insulated from the semiconductor body (48; 68) by an electrical insulation region (52; 80). The electrical insulation region is a multilayer comprising: a first insulating layer (102), of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer (104) on the first insulating layer (102), of a Hafnium Oxide; and a third insulating layer (106) on the second insulating layer (104), of an Aluminum Oxide.

公开(公告)号：EP3496153A1

公开(公告)日：2019-06-12

申请号：EP18206678.7

申请日：2018-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： ZANETTI, Edoardo ,  RASCUNA', Simone ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio ,  FRAGAPANE, Leonardo ,  TRINGALI, Cristina

IPC: H01L29/872 ,  H01L21/329 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

Abstract: A manufacturing method of an electronic device (50), comprising the steps of: forming a drift layer (32) of an N type; forming a trench (38) in the drift layer (32); forming an edge-termination structure (42) alongside the trench (38) by implanting dopant species of a P type; and forming a depression region between the trench (38) and the edge-termination structure (42) by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection (32c) with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：EP3425676A1

公开(公告)日：2019-01-09

申请号：EP18181848.5

申请日：2018-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  RASCUNA', Simone

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/872

Abstract: An integrated MOSFET device (20) formed in a body (22), of silicon carbide and with a first conductivity type. The body accommodates a first body region (23), with a second conductivity type; a JFET region (35) adjacent to the first body region (23); a first source region (24), with the first conductivity type, extending into the interior of the first body region; an implanted structure (40), with the second conductivity type, extending into the interior of the JFET region (35). An isolated gate structure (39) lies partially over the first body region (23), the first source region (24) and the JFET region (35). A first metallization layer (43) extends over the first surface (22A) and forms, in direct contact with the implanted structure (40) and with the JFET region (35), a JBS diode.

公开(公告)号：EP3136447A1

公开(公告)日：2017-03-01

申请号：EP16162000.0

申请日：2016-03-23

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  RASCUNA', Simone

IPC: H01L29/872 ,  H01L21/329 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/6606 ,  H01L29/66143

Abstract: A switching device including: a body (2) of semiconductor material, which has a first conductivity type and is delimited by a front surface (S a ); a contact layer (12) of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions (20), which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

Abstract translation: 一种开关装置，包括：具有第一导电类型并由前表面（S a）限定的半导体材料的主体（2）; 第一导电材料的接触层（12），其与前表面接触地延伸; 以及多个埋置区域（20），其具有第二导电类型并且布置在半导体主体内，距接触层一定距离处。

公开(公告)号：EP4307384A3

公开(公告)日：2024-02-07

申请号：EP23181494.8

申请日：2023-06-26

Applicant: STMicroelectronics S.r.l.

Inventor： CAMALLERI, Cateno Marco ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A power MOSFET device (1) comprises a semiconductor body (3) having a first main surface (3a). The semiconductor body (3) includes an active area (7) facing the first main surface (3a). The power MOSFET device (1) comprises an isolated-gate structure (15), which extends over the active area (7) and includes a gate-oxide layer (12), which is made of insulating material and extends over the first main surface (3a), and a gate region (24) buried in the gate-oxide layer (12) so as to be electrically insulated from the semiconductor body (3). The gate region (24) comprises a gate layer (14) of polysilicon and at least one first silicide region (25a) and one second silicide region (25b), which extend in the gate layer (14) so as to face a top surface (14a) of the gate layer (14) and to be arranged alongside one another and spaced apart from one another in a first plane (XY).

公开(公告)号：EP4040498A1

公开(公告)日：2022-08-10

申请号：EP22154844.9

申请日：2022-02-02

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA', Simone ,  BELLOCCHI, Gabriele ,  ZANETTI, Edoardo ,  SAGGIO, Mario Giuseppe

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  H01L29/872

Abstract: The vertical conduction electronic device (50) is formed by a body (55) of wide-bandgap semiconductor material having a first conductivity type and a surface (55A), which defines a first direction (Y) and a second direction (X), wherein the body has a drift region (59, 59A, 59B). The electronic device is further formed by a plurality of superficial implanted regions (62) having a second conductivity type, which extend in the drift region from the surface and delimit between them, in the drift region, at least one superficial portion (68) facing the surface; by at least one deep implanted region (65) having the second conductivity type, which extends in the drift region, at a distance from the surface of the body; and by a metal region (80), which extends on the surface of the body, in Schottky contact with the superficial portion (68) of the drift region.

公开(公告)号：EP3945606A1

公开(公告)日：2022-02-02

申请号：EP21187913.5

申请日：2021-07-27

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA', Simone ,  SAGGIO, Mario Giuseppe

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16 ,  H01L21/329

Abstract: Merged-PiN-Schottky, MPS, device (50) comprising: a substrate (53) of SiC with a first conductivity; a drift layer (52) of SiC with the first conductivity, on the substrate (53); an implanted region (59') with a second conductivity, extending at a top surface (52a) of the drift layer (52) to form a junction-barrier, JB, diode (59) with the substrate (53); and a first electrical terminal (58) in ohmic contact with the implanted region (59') and in direct contact with the top surface (52a) to form a Schottky diode (62) with the drift layer (52). The JB diode (59) and the Schottky diode (62) are alternated to each other along an axis (X): the JB diode (59) has a minimum width parallel to the axis (X) with a first value (d 1 ), and the Schottky diode (62) has a maximum width parallel to the axis (X) with a second value (d 2 ) smaller than, or equal to, the first value (d 1 ). A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.