公开(公告)号：WO2007122646A1

公开(公告)日：2007-11-01

申请号：PCT/IT2006/000273

申请日：2006-04-21

Applicant: STMICROELECTRONICS S.R.L. ,  GUARNERA, Alfio ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： GUARNERA, Alfio ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/10 ,  H01L29/739 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L29/0634 ,  H01L21/2003 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a power semiconductor device (25; 35) envisages the steps of: providing a body of semiconductor material (3) having a top surface (4) and having a first conductivity; forming columnar regions (6) having a second type of conductivity within the body of semiconductor material (3), and surface extensions (10) of the columnar regions (6) above the top surface (4); and forming doped regions (19, 20) having the second type of conductivity, in the proximity of the top surface (4) and in contact with the columnar regions (6). The doped regions (19, 20) are formed at least partially within the surface extensions (10) of the columnar regions (6); the surface extensions (10) and the doped regions (20) have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Abstract translation: 一种用于制造功率半导体器件（25; 35）的工艺设想了以下步骤：提供具有顶表面（4）并具有第一导电性的半导体材料体（3）; 在所述半导体材料（3）的主体内形成具有第二导电类型的柱状区域（6）以及所述顶表面（4）上方的所述柱状区域（6）的表面延伸部（10）。 以及在所述顶表面（4）附近形成具有所述第二导电类型的掺杂区域（19,20）并与所述柱状区域（6）接触。 掺杂区域（19,20）至少部分地形成在柱状区域（6）的表面延伸部分（10）内; 表面延伸部（10）和掺杂区域（20）具有非平面的表面图案，特别是具有大致V形的凹槽。

公开(公告)号：EP3496153A1

公开(公告)日：2019-06-12

申请号：EP18206678.7

申请日：2018-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： ZANETTI, Edoardo ,  RASCUNA', Simone ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio ,  FRAGAPANE, Leonardo ,  TRINGALI, Cristina

IPC: H01L29/872 ,  H01L21/329 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

Abstract: A manufacturing method of an electronic device (50), comprising the steps of: forming a drift layer (32) of an N type; forming a trench (38) in the drift layer (32); forming an edge-termination structure (42) alongside the trench (38) by implanting dopant species of a P type; and forming a depression region between the trench (38) and the edge-termination structure (42) by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection (32c) with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：EP4254511A1

公开(公告)日：2023-10-04

申请号：EP23161989.1

申请日：2023-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： CASCINO, Salvatore ,  GUARNERA, Alfio ,  SAGGIO, Mario Giuseppe

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: Electronic device comprising: a semiconductor body (8, 10) having a first electrical conductivity (N) and provided with a front side (1a); an active area (4) of the semiconductor body, accommodating the source (12) and gate (14) regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; and an edge region (6) of the electronic device, surrounding the active area (4) and accommodating at least in part: i) an edge termination region (20), having a second electrical conductivity (P) opposite to the first electrical conductivity (N), extending into the semiconductor body at the front side (1a); and ii) a gate connection terminal (24) of conductive material, electrically coupled to the gate region (14), extending on the front side (1a) partially superimposed on the edge termination region (20) and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region (20) .

公开(公告)号：EP4036957A1

公开(公告)日：2022-08-03

申请号：EP22153333.4

申请日：2022-01-25

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  FRAZZETTO, Alessia Maria ,  ZANETTI, Edoardo ,  GUARNERA, Alfio

IPC: H01L21/336 ,  H01L29/16 ,  H01L21/04 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417

Abstract: The vertical conduction MOSFET device (100) is formed by a body (105) of silicon carbide, which has a first conductivity type and a face (105A); by a metallization region (140), which extends on the face of the body; by a body region (115) of a second conductivity type different from the first conductivity type, which extends in the body, from the face of the body, along a first direction (Y) parallel to the face and along a second direction (Z) transverse to the face; and by a source region (120) of the first conductivity type, which extends towards the inside of the body region, from the face of the body. The source region has a first portion (120A) and a second portion (120B), wherein the first portion has a first doping level and extends in direct electrical contact with the metallization region, wherein the second portion has a second doping level and extends in direct electrical contact with the first portion of the source region, and wherein the second doping level is lower than the first doping level.

公开(公告)号：EP4177960A1

公开(公告)日：2023-05-10

申请号：EP22204133.7

申请日：2022-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： CASCINO, Salvatore ,  GUARNERA, Alfio ,  SAGGIO, Mario Giuseppe

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06

Abstract: A semiconductor power device has a maximum nominal voltage and includes: a first conduction terminal (1a) and a second conduction terminal (lb); a semiconductor body (2), containing silicon carbide and having a first conductivity type; body wells (7) having a second conductivity type, housed in the semiconductor body and separated from one another by a body distance (LB); source regions housed in the body wells (7); and floating pockets (20) having the second conductivity type, formed in the semiconductor body (2) at a distance from the body wells (7) between a first face (2a) and a second face (2b) of the semiconductor body (2). The floating pockets (20) are shaped and arranged relative to the body wells (7) so that a maximum intensity of electrical field around the floating pockets (20) is greater than a maximum intensity of electrical field around the body wells (7) at least for values of an operating voltage (VDS) between the first conduction terminal (1a) and the second conduction terminal (1b) greater than a threshold voltage, the threshold voltage being less than the maximum nominal voltage.

公开(公告)号：EP4047664A1

公开(公告)日：2022-08-24

申请号：EP22155166.6

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio ,  CAMALLERI, Cateno Marco

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/336

Abstract: A vertical-conduction MOSFET device (50) formed in a body (55) of silicon carbide having a first and a second face (52A, 52B) and a peripheral zone (87). A drain region (57), of a first conductivity type, extends in the body (55) between the two faces. A body region (60), of a second conductivity type, extends in the body from the first face (55A), and a source region (65), having the first conductivity type, extends to the inside of the body region (60) from the first face (55A) of the body. An insulated gate region (70) extends on the first face of the body and comprises a gate conductive region (72). An annular connection region (86), of conductive material, is formed within a surface edge structure extending on the first face (55A) of the body (55), in the peripheral zone (87). The gate conductive region (72) and the annular connection region (86) are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.

公开(公告)号：EP3930007A1

公开(公告)日：2021-12-29

申请号：EP21180931.4

申请日：2021-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  MAGRI', Angelo ,  ZANETTI, Edoardo ,  GUARNERA, Alfio

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36

Abstract: Electronic device (100) comprising: a semiconductor body (102) of silicon carbide; a body region (105) at a first surface of the semiconductor body; a source region (108) in the body region (105); a drain region (104) at a second surface of the semiconductor body (102); a doped region (120) extending seamlessly at the entire first surface (102a) of the semiconductor body (102) and including one or more first sub-regions (121) having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

公开(公告)号：EP4307384A3

公开(公告)日：2024-02-07

申请号：EP23181494.8

申请日：2023-06-26

Applicant: STMicroelectronics S.r.l.

Inventor： CAMALLERI, Cateno Marco ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A power MOSFET device (1) comprises a semiconductor body (3) having a first main surface (3a). The semiconductor body (3) includes an active area (7) facing the first main surface (3a). The power MOSFET device (1) comprises an isolated-gate structure (15), which extends over the active area (7) and includes a gate-oxide layer (12), which is made of insulating material and extends over the first main surface (3a), and a gate region (24) buried in the gate-oxide layer (12) so as to be electrically insulated from the semiconductor body (3). The gate region (24) comprises a gate layer (14) of polysilicon and at least one first silicide region (25a) and one second silicide region (25b), which extend in the gate layer (14) so as to face a top surface (14a) of the gate layer (14) and to be arranged alongside one another and spaced apart from one another in a first plane (XY).

公开(公告)号：EP3800660A1

公开(公告)日：2021-04-07

申请号：EP20198891.2

申请日：2020-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA, Simone ,  CHIBBARO, Claudio ,  GUARNERA, Alfio ,  SAGGIO, Mario Giuseppe ,  LIZIO, Francesco

IPC: H01L23/31

Abstract: An electronic power device (25) is provided with: a substrate (2) of silicon carbide (SiC), having a front surface (2a) and a rear surface (2b), which lie in a horizontal plane (xy) and are opposite to one another along a vertical axis (z), the substrate including an active area (A'), provided in which are a number of doped regions (4), and an edge area (A"), which is not active, distinct from and surrounding the active area (A'); a dielectric region (8a) arranged above the front surface (2a), at least at the edge area (A"); and a passivation layer (20) arranged above the front surface (2a) of the substrate (2), in contact with the dielectric region (8a) in the edge area (A"). The passivation layer (20) comprises at least one anchorage region (22) that extends throughout the thickness of the dielectric region (8a) at the edge area (A"), such as to define a mechanical anchorage for the passivation layer (20).

公开(公告)号：EP4307384A2

公开(公告)日：2024-01-17

申请号：EP23181494.8

申请日：2023-06-26

Applicant: STMicroelectronics S.r.l.

Inventor： CAMALLERI, Cateno Marco ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A power MOSFET device (1) comprises a semiconductor body (3) having a first main surface (3a). The semiconductor body (3) includes an active area (7) facing the first main surface (3a). The power MOSFET device (1) comprises an isolated-gate structure (15), which extends over the active area (7) and includes a gate-oxide layer (12), which is made of insulating material and extends over the first main surface (3a), and a gate region (24) buried in the gate-oxide layer (12) so as to be electrically insulated from the semiconductor body (3). The gate region (24) comprises a gate layer (14) of polysilicon and at least one first silicide region (25a) and one second silicide region (25b), which extend in the gate layer (14) so as to face a top surface (14a) of the gate layer (14) and to be arranged alongside one another and spaced apart from one another in a first plane (XY).