公开(公告)号：EP1028379B1

公开(公告)日：2003-05-07

申请号：EP99830070.1

申请日：1999-02-10

Applicant: STMicroelectronics S.r.l.

Inventor： Modelli, Alberto

IPC: G06F11/10

CPC classification number: G06F11/1072 ,  G11C11/5621 ,  G11C29/00

公开(公告)号：EP1178540A1

公开(公告)日：2002-02-06

申请号：EP00830546.8

申请日：2000-07-31

Applicant: STMicroelectronics S.r.l.

Inventor： Esseni, David ,  Selmi, Luca ,  Bez, Roberto ,  Modelli, Alberto

IPC: H01L29/788 ,  H01L27/115

CPC classification number: H01L29/66825 ,  G11C16/0416 ,  H01L27/11521 ,  H01L29/7885

Abstract: The memory cell (1) is formed in a body (3) of a P-type semiconductor material forming a channel region (25) and housing N-type drain and source regions (15, 12) at two opposite sides of the channel region (25). A floating gate region (5) extends above the channel region (25). A P-type charge injection region (18) extends in the body (3) contiguously to the drain region (15), at least in part between the channel region (25) and the drain region (15). An N-type base region (21) extends between the drain region (15), the charge injection region (18), and the channel region (25). The charge injection region (18) and the drain region (15) are biased by special contact regions (19, 16) so as to forward bias the PN junction formed by the charge injection region (18) and the base region (21). The holes thus generated in the charge injection region (18) are directly injected through the base region (21) into the body (3), where they generate, by impact, electrons that are injected towards the floating gate region (5).

Abstract translation: 存储单元（1）形成在形成沟道区域（25）的P型半导体材料的主体（3）中，并且在沟道区域的两个相对侧容纳N型漏极和源极区域（15,12） （25）。 浮动栅极区域（5）在沟道区域（25）的上方延伸。 P型电荷注入区域（18）至少部分地在沟道区域（25）和漏极区域（15）之间连续延伸到漏极区域（15）。 N型基极区域（21）在漏极区域（15），电荷注入区域（18）和沟道区域（25）之间延伸。 电荷注入区域（18）和漏极区域（15）被特殊接触区域（19,16）偏置，以便对由电荷注入区域（18）和基极区域（21）形成的PN结进行正向偏压。 这样在电荷注入区域（18）中产生的空穴通过基极区域（21）直接注入到体（3）中，在那里它们通过冲击产生被注入到浮动栅极区域（5）的电子。

公开(公告)号：EP1074995A1

公开(公告)日：2001-02-07

申请号：EP99830501.5

申请日：1999-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： Torelli, Guido ,  Modelli, Alberto ,  Manstretta, Alessandro

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5628

Abstract: When programming, for each programming pulse, a threshold voltage whose value is increased with respect to the previous programming pulse is applied to the gate terminal of each cell to be programmed. After an initial step, the increase of threshold voltage of the cell being programmed becomes equal to the applied gate voltage increase (ΔV GP ). In order to reduce the global programming time, keeping a small variability interval of threshold voltages associated with each level, to pass from a threshold level to a following one, each cell to be programmed is supplied with a plurality of consecutive pulses without verify (107-109), until it immediately goes below the voltage level to be programmed, and then a verify step (110) is performed, followed by subsequent programming and verify steps (112, 110, 117, 118) until the cell to be programmed reaches the desired threshold value.

Abstract translation: 当编程时，对于每个编程脉冲，其值相对于先前编程脉冲增加的阈值电压被施加到要编程的每个单元的栅极端子。 在初始步骤之后，被编程的单元的阈值电压的增加等于施加的栅极电压增加（DELTA VGP）。 为了减少全局编程时间，保持与每个电平相关联的阈值电压的小变化间隔从阈值电平传递到随后的每个要编程的每个单元被提供多个连续的脉冲而不验证（107 -109），直到其立即低于要编程的电压电平，然后执行验证步骤（110），随后进行后续编程和验证步骤（112,110,117,118），直到待编程的单元达到 所需的阈值。

公开(公告)号：EP1074995B1

公开(公告)日：2005-10-26

申请号：EP99830501.5

申请日：1999-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： Torelli, Guido ,  Modelli, Alberto ,  Manstretta, Alessandro

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5628

公开(公告)号：EP1028379A1

公开(公告)日：2000-08-16

申请号：EP99830070.1

申请日：1999-02-10

Applicant: STMicroelectronics S.r.l.

Inventor： Modelli, Alberto

IPC: G06F11/10

CPC classification number: G06F11/1072 ,  G11C11/5621 ,  G11C29/00

Abstract: The method for correction comprises the step of executing the following steps, for each set of bits in the binary word stored in a single memory cell: a) assigning, to each single error, an error code which is not assigned to other errors; b) for each sub-set of multiple errors, carrying out the following steps: b1) assigning to the sub-set of multiple errors an error code, which is dependent on the error codes assigned to each of the individual errors in the sub-set itself; b2) checking whether the error code assigned to the said sub-set has already been assigned to other errors; b3) if the error code assigned to the said sub-set has already been assigned to other errors, carrying out the following steps: b31) rejecting the error code assigned to the said sub-set, and at least one of the error codes assigned to one of the single errors in the sub-set itself; b32) assigning to the single error assigned to the error code rejected, a new error code, which is not assigned to other errors; and b33) repeating the steps from b1) to b3), until the error code assigned to the sub-set of multiple errors is not assigned to other errors.

Abstract translation: 用于校正的方法包括执行以下步骤，对于在存储在单个存储器单元中的二进制字中的每个位集合的步骤：1）分配给每个单个错误，错误代码的所有未分配给其他的错误; b）对于每个子集的多个错误的，执行以下步骤：b1）中分配给所述子集的多个错误的错误代码，所有这些依赖于在子分配给每个单独的错误的错误代码 为自己设定; b2）中检查是否分配给所述子集的错误代码已被分配给其他的错误; B3）如果分配给所述子集的错误代码已被分配给其他的错误，进行以下步骤：B31）拒绝分配给所述子集的误差代码，并分配错误代码中的至少一个 在单个错误之一的子集本身; B32）分配给分配给拒绝错误代码，一个新的错误代码的单个错误，所有这一切都没有分配给其他错误; 和B33）重复从B1至B3的步骤）），直到分配给多个错误的子集中的错误代码不被分配给其他错误。