Ic of an integrator with enhanced stability and stabilization method
    1.
    发明公开
    Ic of an integrator with enhanced stability and stabilization method 有权
    IC eines Integrator mit erweiterterStabiilitätund Stabilisierungsverfahren

    公开(公告)号:EP2306642A1

    公开(公告)日:2011-04-06

    申请号:EP10179881.7

    申请日:2010-09-27

    CPC classification number: H03H11/0422 Y10T29/49124

    Abstract: An architecture of an integrator has an input transconductance amplifier Gi having an output resistance adjustable independently from the transconductance gain Gi, through a dedicated control signal, and includes also a matched transconductance amplifier Gi2 having an adjustable gain and an output resistance matched with that of the first transconductance amplifier Gi and adjusted by the same dedicated control signal. A reference current is forced through the matched output resistance and the dedicated control signal is generated such to keep constant the output voltage of the matched transconductance amplifier.
    A method of stabilization against PVT variations of the integrated circuit of an integrator is also disclosed.

    Abstract translation: 积分器的架构具有通过专用控制信号具有可独立于跨导增益Gi调节的输出电阻的输入跨导放大器Gi,并且还包括具有可调节增益的匹配跨导放大器Gi2和与 第一跨导放大器Gi并由相同的专用控制信号调整。 参考电流被强制通过匹配的输出电阻,并且产生专用控制信号以使匹配的跨导放大器的输出电压保持恒定。 还公开了对积分器的集成电路的PVT变化进行稳定化的方法。

    Integrated circuit with highly efficient junction insulation
    2.
    发明公开
    Integrated circuit with highly efficient junction insulation 失效
    Integrierte Schaltung mit hocheffizienter隔离性PN-Übergang

    公开(公告)号:EP0915508A1

    公开(公告)日:1999-05-12

    申请号:EP97830507.6

    申请日:1997-10-10

    CPC classification number: H01L21/761

    Abstract: There is described an integrated circuit with junction insulation on a substrate (10) of semiconductor material comprising active regions (11, 11', 11'') of a first type of conductivity (n), insulation regions (30-33) which separate the junction-forming active regions from one another and from the substrate and means of electrical contact for reverse-biasing the junctions. In order to obtain highly efficient insulation, at least one (11) of the active regions is separated from the active regions adjacent to it (11') and from the substrate (10) by insulation regions (30-33) which form an inner insulation shell, consisting of regions (30, 31) of conductivity of a second type (p), opposite to the first type, which contains the active region (11) and an outer insulation shell, consisting of regions (32, 33) of the first type of conductivity (n) which contains the inner insulation shell.

    Abstract translation: 描述了在半导体材料的衬底(10)上具有结绝缘的集成电路,其包括第一类型导电(n)的有源区(11,11',11“),绝缘区(30-33),其分离 所述接合形成有源区彼此和所述衬底以及用于反向偏置所述接点的电接触装置。 为了获得高效绝缘,通过绝缘区域(30-33)将至少一个有源区域与其邻近的有源区(11')和基板(10)分离,形成内部 绝缘壳体,包括与第一类型相反的第二类型(p)的导电性的区域(30,31),所述第一类型包含有源区域(11)和外部绝缘壳体,所述外部绝缘壳体由以下区域(32,33)组成: 第一种导电性(n)包含内绝缘壳。

    Phase detector and method of generating a differential signal representative of a phase-shift
    4.
    发明公开
    Phase detector and method of generating a differential signal representative of a phase-shift 审中-公开
    相位检测器和用于产生代表的相移信号相关联的方法

    公开(公告)号:EP1473828A1

    公开(公告)日:2004-11-03

    申请号:EP03425274.2

    申请日:2003-04-30

    CPC classification number: H03L7/085 H03D13/00

    Abstract: A phase detector input with a generally oscillating signal, and with a clock signal for outputting a differential signal representing the phase difference between the oscillating signal and the clock signal, comprises

    a first differential pair of transistors (Q3,Q4) driven by the clock signal and by its inverted replica (CK and CKN) for generating the differential signal (OUT+,OUT-) corresponding to the currents respectively flowing in the transistors of the first differential pair;
    at least an auxiliary differential pair of transistors (Q1,Q2) driven by the oscillating signal and its inverted replica (DAT and DATN) having its common current node coupled to corresponding current nodes of the first differential pair;
    a current generator (Ipd) biasing all the differential pairs.
    If there are long periods of time during which the oscillating signal does not switch, the precision of the frequency of the recovered clock may worsen progressively. This problem is solved by providing the phase detector with a feedback loop for regulating the current delivered by the current generator that monitors the transition density of the generally oscillating input signal and increases the bias current of the differential pairs when the transition density decreases. The output differential signal is thus generated with a greater gain thus making the VCO that is present downstream, adjust more promptly the frequency of the recovered clock.

    Abstract translation: 与基因的反弹振荡信号的相位检测器输入端,并具有用于输出铃声的时钟信号表示所述振荡信号和所述时钟信号之间的相位差的差分信号,包括:第一差分对由时钟信号驱动晶体管(Q3,Q4)的 和由用于生成所述差分信号反相其复制品(CK和CKN)(OUT +,OUT-)对应于所述第一差分对的晶体管分别流动的电流; 至少由所述振荡信号和其反相复制品(DAT和DATN)驱动的辅助差分对晶体管(Q1,Q2),其具有其常见的当前节点耦合到对应的所述第一差动对的电流节点; 电流发生器(LPD)偏置所有的差分对。 如果存在的时间,这期间,所述振荡信号不切换长时间,再生时钟脉冲的频率的精度可逐渐恶化。 这种麻烦是通过提供与一个反馈环路相位检测器,用于调节由所述电流发生器提供的电流做监视基因反弹振荡输入信号的转变密度解决并增加了差分对的偏置电流。当过渡密度降低。 差分输出信号因此具有更大的增益从而使VCO确实产生存在下游,调整更迅速地恢复的时钟的频率。

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