Abstract:
An architecture of an integrator has an input transconductance amplifier Gi having an output resistance adjustable independently from the transconductance gain Gi, through a dedicated control signal, and includes also a matched transconductance amplifier Gi2 having an adjustable gain and an output resistance matched with that of the first transconductance amplifier Gi and adjusted by the same dedicated control signal. A reference current is forced through the matched output resistance and the dedicated control signal is generated such to keep constant the output voltage of the matched transconductance amplifier. A method of stabilization against PVT variations of the integrated circuit of an integrator is also disclosed.
Abstract:
There is described an integrated circuit with junction insulation on a substrate (10) of semiconductor material comprising active regions (11, 11', 11'') of a first type of conductivity (n), insulation regions (30-33) which separate the junction-forming active regions from one another and from the substrate and means of electrical contact for reverse-biasing the junctions. In order to obtain highly efficient insulation, at least one (11) of the active regions is separated from the active regions adjacent to it (11') and from the substrate (10) by insulation regions (30-33) which form an inner insulation shell, consisting of regions (30, 31) of conductivity of a second type (p), opposite to the first type, which contains the active region (11) and an outer insulation shell, consisting of regions (32, 33) of the first type of conductivity (n) which contains the inner insulation shell.
Abstract:
A linear phase detection (PD) has a variable gain that is regulated in function of the monitored transition density of the input signal (DAT). The transition density is sensed by a circuit (Q3', Q4', R2, C2, Ipd) that generates a signal (V2) corresponding to a time averaged common mode component of the differential current signal (OUT+, OUT-) output by the phase detector (PD).
Abstract:
A phase detector input with a generally oscillating signal, and with a clock signal for outputting a differential signal representing the phase difference between the oscillating signal and the clock signal, comprises
a first differential pair of transistors (Q3,Q4) driven by the clock signal and by its inverted replica (CK and CKN) for generating the differential signal (OUT+,OUT-) corresponding to the currents respectively flowing in the transistors of the first differential pair; at least an auxiliary differential pair of transistors (Q1,Q2) driven by the oscillating signal and its inverted replica (DAT and DATN) having its common current node coupled to corresponding current nodes of the first differential pair; a current generator (Ipd) biasing all the differential pairs. If there are long periods of time during which the oscillating signal does not switch, the precision of the frequency of the recovered clock may worsen progressively. This problem is solved by providing the phase detector with a feedback loop for regulating the current delivered by the current generator that monitors the transition density of the generally oscillating input signal and increases the bias current of the differential pairs when the transition density decreases. The output differential signal is thus generated with a greater gain thus making the VCO that is present downstream, adjust more promptly the frequency of the recovered clock.