公开(公告)号：EP2280412A2

公开(公告)日：2011-02-02

申请号：EP10184095.7

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81C1/00

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A semiconductor substrate comprising at least a buried insulating cavity (10b, 10d) and comprising:
- a semiconductor substrate (7) having a first type of concentration and having a plurality of trenches (8, 10),
- a surface layer (7a, 9a) on said semiconductor substrate (7) in order to close superficially said plurality of trenches (8, 10) forming said at least a buried insulating cavity (10b, 10d);
- a first semiconductor material layer (9) on said surface layer (7a, 9a) having the same first type of concentration as said semiconductor substrate (7), said first semiconductor material layer (9) comprising at least a trench (11) which is in communication with said at least a buried insulating cavity (10b, 10d).

Abstract translation: 1.一种半导体衬底，包括至少一个掩埋绝缘腔（10b，10d），并且包括：具有第一类型的半导体衬底（7）并具有多个沟槽（8,10）， - 表面层（7a， 以形成所述至少一个掩埋绝缘腔（10b，10d）的所述多个沟槽（8,10）的表面封闭; - 在所述表面层（7a，9a）上具有与所述半导体衬底（7）相同的第一类型的第一半导体材料层（9），所述第一半导体材料层（9）至少包括沟槽（11），所述沟槽 与所述至少一个掩埋绝缘腔（10b，10d）连通。

公开(公告)号：EP1427010A1

公开(公告)日：2004-06-09

申请号：EP02425742.0

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81B1/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A method for manufacturing a semiconductor substrate (7) of a first concentration type is described, which comprises at least a buried insulating cavity (10b, 10d), comprising the following steps:

form on the semiconductor substrate (7) a plurality of trenches (8, 10),
form a surface layer (7a, 9a) on the semiconductor substrate in order to close superficially the plurality of trenches (8, 10) forming in the meantime at least a buried cavity (10b) in correspondence with the surface-distal end of the trenches (8, 10).

Devices manufactured with the method according to the invention are also described.

Abstract translation: 一种用于制造（7）的第一浓度类型的，描述了一种半导体衬底的方法，其包括至少一个掩埋绝缘腔（10B，10D）包括以下步骤：形式在半导体基片（7）的沟槽的多个（ 8，10），形成在半导体衬底的表面层（图7A，图9A）以闭合表面上的沟槽（8的多元性，10）（图10b），其与所述表面对应的平均时间中形成至少一个掩埋空腔 沟槽（8，10）的远端。 因此与方法雅丁本发明制造设备进行了描述。

公开(公告)号：EP2280412A3

公开(公告)日：2011-02-16

申请号：EP10184095.7

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81C1/00 ,  H01L21/302 ,  H01L21/306

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A semiconductor substrate comprising at least a buried insulating cavity (10b, 10d) and comprising:
- a semiconductor substrate (7) having a first type of concentration and having a plurality of trenches (8, 10),
- a surface layer (7a, 9a) on said semiconductor substrate (7) in order to close superficially said plurality of trenches (8, 10) forming said at least a buried insulating cavity (10b, 10d);
- a first semiconductor material layer (9) on said surface layer (7a, 9a) having the same first type of concentration as said semiconductor substrate (7), said first semiconductor material layer (9) comprising at least a trench (11) which is in communication with said at least a buried insulating cavity (10b, 10d).