公开(公告)号：EP1130631A1

公开(公告)日：2001-09-05

申请号：EP00830148.3

申请日：2000-02-29

Applicant: STMicroelectronics S.r.l.

Inventor： Erratico, Pietro ,  Sacchi, Enrico ,  Villa, Flavio ,  Barlocchi, Gabriele ,  Corona, Pietro

IPC: H01L21/308

CPC classification number: B81C1/00404

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer (10), a holed mask (16) having a lattice structure and comprising a plurality of openings (18) each having a substantially square shape and a side with an inclination of 45° with respect to the flat (110) of the wafer; carrying out an anisotropic etch in TMAH of the wafer (10), using said holed mask (16), thus forming a cavity (20), the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapour deposition (CVD) using TEOS, thus forming a TEOS layer (24) which completely closes the openings of the holed mask (16) and defines a diaphragm (26) overlying the cavity (20) and on which a suspended integrated structure can subsequently be manufactured.

Abstract translation: 该方法包括以下步骤：在半导体材料晶片（10）的顶部上形成具有格子结构的孔掩模（16），并且包括多个开口（18），每个开口（18）均具有大致正方形的形状， 相对于晶片的平面（110）为45°; 使用所述带孔掩模（16）在晶片（10）的TMAH中进行各向异性蚀刻，从而形成空腔（20），其横截面具有倒立的等腰梯形的形状; 并使用TEOS进行化学气相沉积（CVD），由此形成TEOS层（24），该TEOS层完全封闭了孔罩（16）的开口，并且限定了覆盖空腔（20）的隔膜（26） 随后可以制造悬浮综合结构。