公开(公告)号：EP2352024A1

公开(公告)日：2011-08-03

申请号：EP11152632.3

申请日：2011-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Ziglioli, Federico Giovanni ,  Maierna, Amedeo ,  Villa, Flavio Francesco ,  Mastromatteo, Ubaldo ,  Barlocchi, Gabriele

IPC: G01N33/00

CPC classification number: G01N33/0009

Abstract: The cartridge-like chemical sensor (140) is formed by a housing (150) having a base (151) and a cover (152) fixed to the base and provided with an input opening (159), an output hole (169) and a channel (165) for a gas to be analyzed. The channel extends in the cover between the input opening and the output hole and faces a printed circuit board (153) carrying an integrated circuit (20) having a sensitive region (16) open toward the channel (165) and of a material capable to bind with target chemicals in the gas to be analyzed. A fan (170) is arranged in the housing, downstream of the integrated device (20), for sucking the gas after being analyzed, and is part of a thermal control system for the integrated circuit.

Abstract translation: 盒式化学传感器（140）由具有基座（151）和固定到基座的盖（152）的壳体（150）形成，并且设置有输入开口（159），输出孔（169）和 用于待分析气体的通道（165）。 通道在输入开口和输出孔之间的盖中延伸并且面向承载具有朝向通道（165）开口的敏感区域（16）的集成电路（20）的印刷电路板（153）和能够 与要分析的气体中的目标化学物质结合。 集成装置（20）的下游配置有风扇（170），用于在分析后吸入气体，并且是集成电路的热控制系统的一部分。

公开(公告)号：EP1732121A1

公开(公告)日：2006-12-13

申请号：EP05425406.5

申请日：2005-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio Francesco ,  Corona, Pietro ,  Barlocchi, Gabriele

IPC: H01L21/762

CPC classification number: H01L21/76264 ,  H01L21/3247

Abstract: In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body (20) of semiconductor material having a front face (20a), a buried cavity (27), which extends at a distance from the front face (20a) and delimits, with the front face (20a), a surface region (28) of the monolithic body (20), the surface region (28) being surrounded by a bulk region (21) and forming a flexible membrane suspended above the buried cavity (27); forming, through the monolithic body (20), at least one access passage (30; 40), which reaches the buried cavity (27); and filling the buried cavity (27) uniformly with an insulating region (35, 36). The surface region (28) is continuous and formed by a single portion of semiconductor material, and the buried cavity (27) is contained and completely insulated within the monolithic body (20); the step of forming at least one access passage (30; 40) is performed after the step of forming a buried cavity (27).

Abstract translation: 在制造SOI晶片的工艺中，设想以下步骤：在具有前表面（20a）的半导体材料的整体式（20）中形成埋藏空腔（27） 面（20a）并且与前表面（20a）分隔开整体式主体（20）的表面区域（28），所述表面区域（28）被块体区域（21）包围并形成悬浮的柔性膜 在掩埋腔（27）之上; 通过所述整体式主体（20）形成到达所述埋入腔（27）的至少一个进入通道（30; 40）; 以及用绝缘区域（35,36）均匀地填充所述掩埋空腔（27）。 表面区域（28）由半导体材料的单个部分连续地形成，并且埋入空腔（27）被包含并在整体式体（20）内完全绝缘; 在形成掩埋腔（27）的步骤之后，进行形成至少一个进入通道（30; 40）的步骤。

公开(公告)号：EP1161985A1

公开(公告)日：2001-12-12

申请号：EP00830400.8

申请日：2000-06-05

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio ,  Mastromatteo, Ubaldo ,  Barlocchi, Gabriele ,  Cattaneo, Mauro

IPC: B01J19/00

CPC classification number: B81C1/00119 ,  B01J19/0093 ,  B01L3/5027 ,  B01L3/502707 ,  B01L7/52 ,  B01L7/525 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/1827 ,  B01L2300/185 ,  B01L2300/1883 ,  B81B2201/0214 ,  B81B2201/051 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/053

Abstract: The microreactor is completely integrated and is formed by a semiconductor body (2) having a surface (4) and housing at least one buried channel (3) accessible from the surface of the semiconductor body (2) through two trenches (21a, 21b). A heating element (10) extends above the surface (4) over the channel (3) and a resist region (18) extends above the heating element and defines an inlet reservoir and an outlet reservoir (19, 20). The reservoirs (19, 20) are connected to the trenches (21a, 21b) and have, in cross-section, a larger area than the trenches. The outlet reservoir (20) has a larger area than the inlet reservoir (19). A sensing electrode (12) extends above the surface (4) and inside the outlet reservoir (20).

Abstract translation: 微反应器是完全呼叫集成并且由一个半导体主体（2）形成具有表面（4）和壳体的至少一个掩埋沟道（3）从所述半导体主体（2）的表面通过两个沟槽访问（21A，21B） ， 的加热元件（10）的表面（4）在所述通道（3）和抗蚀剂区域（18）上方延伸，加热元件的上方延伸，并且限定到入口储槽和出口储槽（19，20）。 储存器（19，20）连接到所述沟槽（21A，21B），并且具有，在横截面中，比沟槽更大的面积。 出口储槽（20）具有比所述入口储（19）大的面积。 的感测电极（12）的表面（4）的上方和出口储槽（20）的内部延伸。

公开(公告)号：EP1009024B1

公开(公告)日：2009-08-26

申请号：EP98830743.5

申请日：1998-12-10

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio

IPC: H01L21/762

CPC classification number: H01L21/76262

公开(公告)号：EP1719993A1

公开(公告)日：2006-11-08

申请号：EP05425306.7

申请日：2005-05-06

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio Francesco ,  Corona, Pietro ,  Barlocchi, Gabriele ,  Baldo, Lorenzo

IPC: G01L7/08 ,  G01L9/00

CPC classification number: G01L9/0045 ,  G01L13/025

Abstract: In a process for manufacturing an integrated differential pressure sensor, the steps of: forming, in a monolithic body (30) of semiconductor material having a first face (30a) and a second face (30b), a cavity (36) extending at a distance from the first face (30a) and delimiting therewith a flexible membrane (37); forming an access passage (42; 42, 44), in fluid communication with the cavity (36); and forming, in the flexible membrane (37), at least one transduction element (38, 72) configured so as to convert a deformation of the flexible membrane (37) into electrical signals. The cavity (36) is formed in a position set at a distance from the second face (30b) and delimits, together with the second face (30b), a portion of the monolithic body (30). In order to form the access passage (42; 42, 44), the monolithic body (30) is etched so as to form an access trench (42) extending through it.

Abstract translation: 在制造集成的差压传感器的过程中，包括以下步骤：在具有第一面（30a）和第二面（30b）的半导体材料的整体体（30）中形成在 距离第一面（30a）的距离并且用其限定柔性膜（37）; 形成与所述空腔（36）流体连通的进入通道（42; 42,44）。 以及在所述柔性膜（37）中形成至少一个构造成将所述柔性膜（37）的变形转换成电信号的换能元件（38,72）。 空腔（36）形成在与第二面（30b）相距一定距离的位置，与第二面（30b）一起界定整体式本体（30）的一部分。 为了形成进入通道（42; 42,44），对整体式主体（30）进行蚀刻，以形成延伸穿过其的通道沟槽（42）。

公开(公告)号：EP1638141A1

公开(公告)日：2006-03-22

申请号：EP04425687.3

申请日：2004-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio Francesco

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/324 ,  H01L21/302

CPC classification number: H01L21/3247 ,  H01L21/3043 ,  H01L21/76251 ,  H01L21/76259

Abstract: Process for manufacturing a wafer using semiconductor processing techniques, wherein a bonding layer (11) is formed on a top surface of a first wafer (10); a deep trench (21) is dug in a substrate (W Si 2) of semiconductor material belonging to a second wafer (20); a top layer (22) of semiconductor material is formed on top of the substrate so as to close the deep trench (21) at the top and form at least one buried cavity (24); the top layer (22) of the second wafer (30) is bonded to the first wafer (10) through the bonding layer (11); the two wafers are subjected to a thermal treatment that causes bonding of at least one portion (42) of the top layer (22) to the first wafer (10) and widening of the buried cavity (24). In this way, the portion (42) of the top layer (22) bonded to the first wafer (10) is separated from the rest (60) of the second wafer (30), to form a composite wafer (50).

公开(公告)号：EP1535665A1

公开(公告)日：2005-06-01

申请号：EP03425771.7

申请日：2003-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Villa, Flavio Francesco ,  Barlocchi, Gabriele

IPC: B01L3/00 ,  B81B3/00

CPC classification number: B01L3/502715 ,  B01L3/5025 ,  B01L3/502707 ,  B01L7/52 ,  B01L2200/027 ,  B01L2200/12 ,  B01L2300/044 ,  B01L2300/0816 ,  B01L2300/1827

Abstract: The microreactor (22) is formed by a sandwich including a first body (1), an intermediate sealing layer (20) and a second body (15). A buried channel (3) extends in the first body (1) and communicates with the surface (12) of the first body (1) through a first and a second apertures (14a, 14b). A first and a second reservoirs (16a, 16b) are formed in the second body (15) and are at least partially aligned with the first and second apertures (14a, 14b). The sealing layer (20) separates the first aperture (14a) from the first reservoir (16a) and the second aperture (14b) from the second reservoir (16b), thereby avoiding contamination of liquids contained in the buried channel from the outside and from any adjacent buried channels (3).

Abstract translation: 微反应器（22）通过夹心包括第一主体（1）至中间密封层（20）和第二本体（15）形成。 掩埋通道（3）在所述第一主体（1）延伸，并且通过第一和第二孔与所述第一主体（1）的表面（12）进行通信（14A，14B）。 第一和第二储存器（16A，16B）形成在所述第二主体（15）和至少部分地与所述第一和第二孔对齐的（14A，14B）。 密封层（20）分离从所述第一储存器（16A）的第一孔（14a）和所述第二孔（14b）的从所述第二储存器（16B），从而避免从外部和从在掩埋沟道所含液体污染 相邻的任何埋入通道（3）。

公开(公告)号：EP1049157A1

公开(公告)日：2000-11-02

申请号：EP99830255.8

申请日：1999-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio ,  Corona, Pietro

IPC: H01L21/764 ,  H01L21/20

CPC classification number: B81C1/00047 ,  B01L3/5027 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/0177 ,  H01L21/764

Abstract: The process comprises the steps of forming, on a monocrystalline-silicon body (11), an etching-aid region (13) of polycrystalline silicon; forming, on the etching-aid region (13), a nucleus region (17) of polycrystalline silicon, surrounded by a protective structure (26) having an opening (22') extending as far as the etching-aid region (13); TMAH-etching the etching-aid region (13) and the monocrystalline body (11), forming a tub shaped cavity (30); removing the top layer (19) of the protective structure (26); and growing an epitaxial layer (33) on the monocrystalline body (11) and the nucleus region (17). The epitaxial layer, of monocrystalline type (33a) on the monocrystalline body (11) and of polycrystalline type (33b) on the nucleus region (17), closes upwardly the etching opening (22'), and the cavity (30) is thus completely embedded in the resulting wafer (34).

Abstract translation: 该方法包括在单晶硅体（11）上形成多晶硅的蚀刻助剂区域（13）的步骤; 在所述蚀刻辅助区域（13）上形成由具有延伸到所述蚀刻助剂区域（13）的开口（22'）的保护结构（26）包围的多晶硅的核区域（17）。 TMAH蚀刻蚀刻助剂区域（13）和单晶体（11），形成桶形空腔（30）; 去除保护结构（26）的顶层（19）; 以及在所述单晶体（11）和所述核区域（17）上生长外延层（33）。 单晶体（11）上的单晶型（33a）外延层和核区域（17）上的多晶型（33b）的外延层向上封闭蚀刻开口（22'），因此空腔（30） 完全嵌入所得晶片（34）中。

公开(公告)号：EP0978872A1

公开(公告)日：2000-02-09

申请号：EP98830476.2

申请日：1998-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: H01L21/762

CPC classification number: H01L21/76294 ,  H01L21/76264 ,  H01L21/76272 ,  H01L21/76289

Abstract: The method comprises the following steps: selective anisotropic etching to form, in the substrate (2'), trenches (16) which extend to a predetermined depth from a major surface of the substrate (2') and between which portions (18) of the substrate (2') are defined, selective isotropic etching to enlarge the trenches (16), starting a predetermined distance from the major surface, thus reducing the thicknesses of the portions (18') of the substrate between adjacent trenches (16), selective oxidation to convert the portions (18') of reduced thickness of the substrate (2') into silicon dioxide (22) and to fill the trenches (16) with silicon dioxide, starting substantially from the said predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate (2').
The method permits great freedom in the selection of the dimensional ratios between the trenches and the pillars and thus enables the necessary crystallographic quality of the epitaxial layer to be achieved, ensuring a continuous buried oxide layer.

Abstract translation: 该方法包括以下步骤：选择性各向异性蚀刻，以在衬底（2'）中形成从衬底（2'）的主表面延伸到预定深度并且在衬底（2'）的哪个部分（18）之间的沟槽（16） 衬底（2'）被限定为选择性各向同性蚀刻以扩大沟槽（16），从主表面开始预定距离，从而减小相邻沟槽（16）之间的衬底部分（18'）的厚度， 选择性氧化以基本上从所述预定距离开始将衬底（2'）的厚度减小的部分（18'）转换成二氧化硅（22）并用二氧化硅填充沟槽（16），并且外延生长 在衬底（2'）的主表面上的硅层。 该方法在选择沟槽和柱之间的尺寸比例方面允许很大的自由度，并且因此能够实现外延层的必要的晶体学质量，确保连续的掩埋氧化物层。

公开(公告)号：EP0957515A1

公开(公告)日：1999-11-17

申请号：EP98830299.8

申请日：1998-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio Francesco

IPC: H01L21/762

CPC classification number: H01L21/7624 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76283

Abstract: The method comprises the steps of: forming doped regions (11, 18) on a monocrystalline substrate (2); growing an epitaxial layer (16); forming trenches (25) in the epitaxial layer as far as the doped regions (18); anodising the doped regions (18) in an electron-galvanic cell to form porous silicon regions (18'); oxidising the porous silicon regions; removing the oxidised porous silicon regions (18'') thereby forming a buried air gap (27); thermally oxidising the wafer (15) thereby growing an oxide region (30) from the walls of the buried air gap (27) and the trenches (25), until the buried air gap and the trenches themselves are completely filled.

Abstract translation: 该方法包括以下步骤：在单晶衬底（2）上形成掺杂区（11,18）; 生长外延层（16）; 在所述外延层中形成直到所述掺杂区域（18）的沟槽（25）; 在电子 - 电池中阳极氧化掺杂区域（18）以形成多孔硅区域（18'）; 氧化多孔硅区域; 去除氧化的多孔硅区域（18“），由此形成掩埋气隙（27）; 热氧化晶片（15），从而从掩埋气隙（27）和沟槽（25）的壁生长氧化物区域（30），直到埋入的气隙和沟槽本身完全充满。