公开(公告)号：EP1043770B1

公开(公告)日：2006-03-01

申请号：EP99830206.1

申请日：1999-04-09

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio

IPC: H01L21/764 ,  H01L21/20 ,  H01L21/306

CPC classification number: H01L21/2007 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/76251 ,  H01L21/76262 ,  H01L21/764

公开(公告)号：EP0948034B1

公开(公告)日：2005-01-05

申请号：EP98830206.3

申请日：1998-04-03

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: H01L21/3065 ,  H01L21/762

CPC classification number: H01L21/3065 ,  H01L21/76248 ,  H01L21/76294

公开(公告)号：EP1073112A1

公开(公告)日：2001-01-31

申请号：EP99830477.8

申请日：1999-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio ,  Barlocchi, Gabriele

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/763

CPC classification number: H01L21/76248 ,  H01L21/76208

Abstract: The process comprises the steps of forming, in a wafer (200) of monocrystalline silicon, first trenches extending between portions of the wafer; etching the substrate (90) to remove the silicon around the first trenches and forming cavities (121) in the substrate (90); covering the walls of the cavities with an epitaxial growth inhibiting layer; growing a monocrystalline epitaxial layer (126) on top of the substrate (90) and the cavities so as to obtain a monocrystalline wafer embedding buried cavities completely surrounded by silicon; forming second trenches (144) extending in the epitaxial layer (126) as far as the cavities; removing the epitaxial growth inhibiting layer; oxidizing the cavities, forming at least one continuous region (127) of buried oxide; depositing a polysilicon layer on the entire surface of the wafer and inside the second trenches (144); removing the polysilicon layer on the surface, leaving filling regions (148) inside the second trenches (144); oxidizing, on the top, portions of said filling regions so as to form field oxide regions (150).

Abstract translation: 该方法包括形成的步骤中，在单晶硅，第一沟槽的晶片的部分之间延伸的一个晶片（200）; 在基片蚀刻所述衬底（90），以去除围绕所述第一沟槽中的有机硅和形成空腔（121）（90）; 覆盖所述腔的壁与在外延生长抑制层; 在基板（90）和所述腔的顶部生长单晶外延层（126），以便获得一个单晶晶片埋嵌入空腔完全通过呼叫硅包围; 形成第二沟槽（144）在所述外延层（126）延伸尽可能所述空腔; 除去外延生长抑制层; 氧化所述空腔中，形成埋入氧化物中的至少一个连续区域（127）; 沉积所述第二沟槽内的晶片的表面上的多晶硅层和整个（144）; 所述第二沟槽内的表面上去除所述多晶硅层，留下填充区（148）（144）; 氧化性，在上面，所述填充区域的部分，以形成场氧化区（150）。

公开(公告)号：EP1001458A1

公开(公告)日：2000-05-17

申请号：EP98830673.4

申请日：1998-11-09

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio

IPC: H01L21/3065

CPC classification number: H01L21/3065

Abstract: The subject of the present invention is a method of forming isotropic recesses in a silicon "wafer".
In particular, the present invention relates to a method for isotropic etching of a silicon wafer, comprising the steps of:

providing a silicon wafer having a protective mask of silicon nitride,
putting the silicon wafer into contact with gaseous hydrogen chloride.

Abstract translation: 本发明的主题是在硅“晶片”中形成各向同性的凹槽的方法。 特别地，本发明涉及一种用于硅晶片的各向同性蚀刻的方法，包括以下步骤：提供具有氮化硅保护掩模的硅晶片，使硅晶片与气态氯化氢接触。

公开(公告)号：EP0948034A1

公开(公告)日：1999-10-06

申请号：EP98830206.3

申请日：1998-04-03

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: H01L21/3065 ,  H01L21/762

CPC classification number: H01L21/3065 ,  H01L21/76248 ,  H01L21/76294

Abstract: The method includes the steps of: on a wafer (1) of monocrystalline semiconductor material, forming a hard mask (9') of an oxidation-resistant material, defining first protective regions (7) covering first portions (21) of the wafer (1); and forming first trenches (10'') in the wafer (1). The first trenches are formed by two etching steps: firstly, the portions (8'') of the wafer (1) not covered by the hard mask (9') are isotropically etched, such as to remove the semiconductor material not only from the portions without a mask, but also partially below the first protective regions (7); then anisotropic etching is carried out. After forming second protective regions (30) incorporating the first protective regions (7), final trenches (16) are formed, and the semiconductor material of wafer (1) is oxidised, except for the portions (21) which are covered by the second protective regions (30), in order to form a continuous oxide region (22); after removal of the second protective regions (30), a monocrystalline layer (23) is grown epitaxially from the non-oxidised portions (21).

Abstract translation: 该方法包括以下步骤：在单晶半导体材料的晶片（1）上形成抗氧化材料的硬掩模（9'），限定覆盖晶片的第一部分（21）的第一保护区域（7） 1）; 以及在所述晶片（1）中形成第一沟槽（10“）。 第一沟槽由两个蚀刻步骤形成：首先，未被硬掩模（9'）覆盖的晶片（1）的部分（8“）被各向同性地蚀刻，例如不仅从 没有掩模的部分，但也部分地在第一保护区域（7）下面; 然后进行各向异性蚀刻。 在形成并入有第一保护区域（7）的第二保护区域（30）之后，形成最终沟槽（16），并且晶片（1）的半导体材料被氧化，除了由第二保护区域 保护区域（30），以形成连续氧化物区域（22）; 在除去第二保护区域（30）之后，从非氧化部分（21）外延生长单晶层（23）。

公开(公告)号：EP0646967B1

公开(公告)日：1999-09-08

申请号：EP93830393.0

申请日：1993-09-27

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio

IPC: H01L29/10 ,  H01L29/735

CPC classification number: H01L29/1004 ,  Y10S148/01

公开(公告)号：EP1009024B1

公开(公告)日：2009-08-26

申请号：EP98830743.5

申请日：1998-12-10

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio

IPC: H01L21/762

CPC classification number: H01L21/76262

公开(公告)号：EP0822579B1

公开(公告)日：2004-07-21

申请号：EP96830437.8

申请日：1996-07-31

Applicant: STMicroelectronics S.r.l.

Inventor： Foroni, Mario ,  Ferrari, Paolo ,  Vigna, Benedetto ,  Villa, Flavio

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/764

CPC classification number: B81C1/00246 ,  B81B2203/0315 ,  B81B2203/033 ,  B81C2201/0109 ,  B81C2203/0728 ,  B81C2203/075 ,  G01L9/0042 ,  G01P15/0802 ,  H01L21/764

公开(公告)号：EP1049157A1

公开(公告)日：2000-11-02

申请号：EP99830255.8

申请日：1999-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio ,  Corona, Pietro

IPC: H01L21/764 ,  H01L21/20

CPC classification number: B81C1/00047 ,  B01L3/5027 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/0177 ,  H01L21/764

Abstract: The process comprises the steps of forming, on a monocrystalline-silicon body (11), an etching-aid region (13) of polycrystalline silicon; forming, on the etching-aid region (13), a nucleus region (17) of polycrystalline silicon, surrounded by a protective structure (26) having an opening (22') extending as far as the etching-aid region (13); TMAH-etching the etching-aid region (13) and the monocrystalline body (11), forming a tub shaped cavity (30); removing the top layer (19) of the protective structure (26); and growing an epitaxial layer (33) on the monocrystalline body (11) and the nucleus region (17). The epitaxial layer, of monocrystalline type (33a) on the monocrystalline body (11) and of polycrystalline type (33b) on the nucleus region (17), closes upwardly the etching opening (22'), and the cavity (30) is thus completely embedded in the resulting wafer (34).

Abstract translation: 该方法包括在单晶硅体（11）上形成多晶硅的蚀刻助剂区域（13）的步骤; 在所述蚀刻辅助区域（13）上形成由具有延伸到所述蚀刻助剂区域（13）的开口（22'）的保护结构（26）包围的多晶硅的核区域（17）。 TMAH蚀刻蚀刻助剂区域（13）和单晶体（11），形成桶形空腔（30）; 去除保护结构（26）的顶层（19）; 以及在所述单晶体（11）和所述核区域（17）上生长外延层（33）。 单晶体（11）上的单晶型（33a）外延层和核区域（17）上的多晶型（33b）的外延层向上封闭蚀刻开口（22'），因此空腔（30） 完全嵌入所得晶片（34）中。

公开(公告)号：EP0978872A1

公开(公告)日：2000-02-09

申请号：EP98830476.2

申请日：1998-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: H01L21/762

CPC classification number: H01L21/76294 ,  H01L21/76264 ,  H01L21/76272 ,  H01L21/76289

Abstract: The method comprises the following steps: selective anisotropic etching to form, in the substrate (2'), trenches (16) which extend to a predetermined depth from a major surface of the substrate (2') and between which portions (18) of the substrate (2') are defined, selective isotropic etching to enlarge the trenches (16), starting a predetermined distance from the major surface, thus reducing the thicknesses of the portions (18') of the substrate between adjacent trenches (16), selective oxidation to convert the portions (18') of reduced thickness of the substrate (2') into silicon dioxide (22) and to fill the trenches (16) with silicon dioxide, starting substantially from the said predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate (2').
The method permits great freedom in the selection of the dimensional ratios between the trenches and the pillars and thus enables the necessary crystallographic quality of the epitaxial layer to be achieved, ensuring a continuous buried oxide layer.

Abstract translation: 该方法包括以下步骤：选择性各向异性蚀刻，以在衬底（2'）中形成从衬底（2'）的主表面延伸到预定深度并且在衬底（2'）的哪个部分（18）之间的沟槽（16） 衬底（2'）被限定为选择性各向同性蚀刻以扩大沟槽（16），从主表面开始预定距离，从而减小相邻沟槽（16）之间的衬底部分（18'）的厚度， 选择性氧化以基本上从所述预定距离开始将衬底（2'）的厚度减小的部分（18'）转换成二氧化硅（22）并用二氧化硅填充沟槽（16），并且外延生长 在衬底（2'）的主表面上的硅层。 该方法在选择沟槽和柱之间的尺寸比例方面允许很大的自由度，并且因此能够实现外延层的必要的晶体学质量，确保连续的掩埋氧化物层。