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    Process for manufacturing a high-quality SOI wafer
    1.
    发明公开
    Process for manufacturing a high-quality SOI wafer 审中-公开
    Herstellungsverfahrenfüreine hochwertige SOI Scheibe

    公开(公告)号：EP1732121A1

    公开(公告)日：2006-12-13

    申请号：EP05425406.5

    申请日：2005-06-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Villa, Flavio Francesco ,  Corona, Pietro ,  Barlocchi, Gabriele

    IPC: H01L21/762

    CPC classification number: H01L21/76264 ,  H01L21/3247

    Abstract: In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body (20) of semiconductor material having a front face (20a), a buried cavity (27), which extends at a distance from the front face (20a) and delimits, with the front face (20a), a surface region (28) of the monolithic body (20), the surface region (28) being surrounded by a bulk region (21) and forming a flexible membrane suspended above the buried cavity (27); forming, through the monolithic body (20), at least one access passage (30; 40), which reaches the buried cavity (27); and filling the buried cavity (27) uniformly with an insulating region (35, 36). The surface region (28) is continuous and formed by a single portion of semiconductor material, and the buried cavity (27) is contained and completely insulated within the monolithic body (20); the step of forming at least one access passage (30; 40) is performed after the step of forming a buried cavity (27).

    Abstract translation: 在制造SOI晶片的工艺中，设想以下步骤：在具有前表面（20a）的半导体材料的整体式（20）中形成埋藏空腔（27） 面（20a）并且与前表面（20a）分隔开整体式主体（20）的表面区域（28），所述表面区域（28）被块体区域（21）包围并形成悬浮的柔性膜 在掩埋腔（27）之上; 通过所述整体式主体（20）形成到达所述埋入腔（27）的至少一个进入通道（30; 40）; 以及用绝缘区域（35,36）均匀地填充所述掩埋空腔（27）。 表面区域（28）由半导体材料的单个部分连续地形成，并且埋入空腔（27）被包含并在整体式体（20）内完全绝缘; 在形成掩埋腔（27）的步骤之后，进行形成至少一个进入通道（30; 40）的步骤。

    Integrated differential pressure sensor and manufacturing process thereof
    3.
    发明公开
    Integrated differential pressure sensor and manufacturing process thereof 审中-公开
    Integrierter Differenzdrucksensor und Verfahren zu dessen Herstellung

    公开(公告)号：EP1719993A1

    公开(公告)日：2006-11-08

    申请号：EP05425306.7

    申请日：2005-05-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Villa, Flavio Francesco ,  Corona, Pietro ,  Barlocchi, Gabriele ,  Baldo, Lorenzo

    IPC: G01L7/08 ,  G01L9/00

    CPC classification number: G01L9/0045 ,  G01L13/025

    Abstract: In a process for manufacturing an integrated differential pressure sensor, the steps of: forming, in a monolithic body (30) of semiconductor material having a first face (30a) and a second face (30b), a cavity (36) extending at a distance from the first face (30a) and delimiting therewith a flexible membrane (37); forming an access passage (42; 42, 44), in fluid communication with the cavity (36); and forming, in the flexible membrane (37), at least one transduction element (38, 72) configured so as to convert a deformation of the flexible membrane (37) into electrical signals. The cavity (36) is formed in a position set at a distance from the second face (30b) and delimits, together with the second face (30b), a portion of the monolithic body (30). In order to form the access passage (42; 42, 44), the monolithic body (30) is etched so as to form an access trench (42) extending through it.

    Abstract translation: 在制造集成的差压传感器的过程中，包括以下步骤：在具有第一面（30a）和第二面（30b）的半导体材料的整体体（30）中形成在 距离第一面（30a）的距离并且用其限定柔性膜（37）; 形成与所述空腔（36）流体连通的进入通道（42; 42,44）。 以及在所述柔性膜（37）中形成至少一个构造成将所述柔性膜（37）的变形转换成电信号的换能元件（38,72）。 空腔（36）形成在与第二面（30b）相距一定距离的位置，与第二面（30b）一起界定整体式本体（30）的一部分。 为了形成进入通道（42; 42,44），对整体式主体（30）进行蚀刻，以形成延伸穿过其的通道沟槽（42）。

    Process for manufacturing buried channels and cavities in semiconductor wafers
    4.
    发明公开
    Process for manufacturing buried channels and cavities in semiconductor wafers 有权
    Halbleiterscheiben的HerstellungsverfahrenfürvergrabeneKanäleundHohlräume

    公开(公告)号：EP1049157A1

    公开(公告)日：2000-11-02

    申请号：EP99830255.8

    申请日：1999-04-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Barlocchi, Gabriele ,  Villa, Flavio ,  Corona, Pietro

    IPC: H01L21/764 ,  H01L21/20

    CPC classification number: B81C1/00047 ,  B01L3/5027 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/0177 ,  H01L21/764

    Abstract: The process comprises the steps of forming, on a monocrystalline-silicon body (11), an etching-aid region (13) of polycrystalline silicon; forming, on the etching-aid region (13), a nucleus region (17) of polycrystalline silicon, surrounded by a protective structure (26) having an opening (22') extending as far as the etching-aid region (13); TMAH-etching the etching-aid region (13) and the monocrystalline body (11), forming a tub shaped cavity (30); removing the top layer (19) of the protective structure (26); and growing an epitaxial layer (33) on the monocrystalline body (11) and the nucleus region (17). The epitaxial layer, of monocrystalline type (33a) on the monocrystalline body (11) and of polycrystalline type (33b) on the nucleus region (17), closes upwardly the etching opening (22'), and the cavity (30) is thus completely embedded in the resulting wafer (34).

    Abstract translation: 该方法包括在单晶硅体（11）上形成多晶硅的蚀刻助剂区域（13）的步骤; 在所述蚀刻辅助区域（13）上形成由具有延伸到所述蚀刻助剂区域（13）的开口（22'）的保护结构（26）包围的多晶硅的核区域（17）。 TMAH蚀刻蚀刻助剂区域（13）和单晶体（11），形成桶形空腔（30）; 去除保护结构（26）的顶层（19）; 以及在所述单晶体（11）和所述核区域（17）上生长外延层（33）。 单晶体（11）上的单晶型（33a）外延层和核区域（17）上的多晶型（33b）的外延层向上封闭蚀刻开口（22'），因此空腔（30） 完全嵌入所得晶片（34）中。

    Process for manufacturing SOI structures
    6.
    发明公开
    Process for manufacturing SOI structures 审中-公开
    Verfahren zur Herstellung von SOI-Strukturen

    公开(公告)号：EP1326272A1

    公开(公告)日：2003-07-09

    申请号：EP01830822.1

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Villa, Flavio ,  Barlocchi, Gabriele ,  Corona, Pietro

    IPC: H01L21/762 ,  H01L21/316 ,  H01L21/306

    CPC classification number: H01L21/76262 ,  H01L21/31662 ,  H01L21/76208

    Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer (1) of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity (9) and laterally delimiting a plurality of pillars of semiconductor material (10); and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate (2); an epitaxial layer (11) is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape; and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings (13a) are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings (13a).

    Abstract translation: 为了制造SOI衬底，进行以下步骤：提供半导体材料的晶片（1）; 在所述晶片内部形成多个通道，所述多个通道形成迷宫腔（9）并横向限定多个半导体材料柱（10）; 并氧化半导体材料的柱以形成掩埋绝缘层。 为了形成迷宫腔，首先在衬底（2）中形成沟槽; 生长外延层（11），其封闭顶部的沟槽; 晶片退火以使柱变形并使其呈现最小能量手柄状形状; 并且去除晶片的周边部分以到达迷宫腔，并且在迷宫腔中形成侧入口（13a）。 通过从侧入口（13a）供给氧化流体来进行氧化。

    Method for the manufacture of electromagnetic radiation reflecting devices
    8.
    发明公开
    Method for the manufacture of electromagnetic radiation reflecting devices 审中-公开
    一种用于生产器件的方法用于反射电磁辐射的

    公开(公告)号：EP1312943A1

    公开(公告)日：2003-05-21

    申请号：EP01830701.7

    申请日：2001-11-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mastromatteo, Ubaldo ,  Corona, Pietro ,  Villa, Flavio ,  Barlocchi, Gabriele

    IPC: G02B5/08 ,  G02B6/36

    CPC classification number: G11B7/1362 ,  G02B5/08 ,  G02B6/4214 ,  G11B7/123 ,  Y10T428/12528

    Abstract: Method for manufacturing electromagnetic radiation reflecting devices (23), said method comprising the steps of:

    a) providing a silicon substrate (1) defined by at least one first free surface (2),
    b) forming on said first surface a layer of protective material provided with an opening which exposes a region of the first free surface (2),
    c)etching the region of the free surface (2) by means of an anisotropic agent to remove at least one portion of the substrate and define a second free surface (16) of the substrate inclined in relation to said first surface. Furthermore, said first free surface (2) is parallel to the crystalline planes {110} of silicon substrate and said step c) comprises a progressing step of the anisotropic agent such that the second free surface (16) resulting from the etching step is parallel to the planes {100} of said substrate (1).

    Abstract translation: （23）所述的方法包括以下步骤：用于制造电磁辐射反射装置的方法：a）提供一个硅衬底（1）由至少一个第一自由表面（2）定义，b）形成于所述第一表面的保护层 在开口设置有材料暴露第一自由表面（2）的一个区域，c）通过各向异性剂的方式蚀刻所述自由表面（2）的区域，以除去所述基板的至少一个部分并限定第二自由 在倾斜于所述第一表面的基板的表面（16）。 进一步，所述第一自由表面（2）是平行于晶面的硅基板的ä110ü和所述步骤c）包括将所述各向异性剂的进展步骤检查做了第二自由表面（16）从蚀刻步骤产生平行于 所说基片的俯视ä100ü（1）。

    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured
    9.
    发明公开
    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured 审中-公开
    一种用于制造半导体晶片具有SOI绝缘沟槽和相应的晶片工艺

    公开(公告)号：EP1881527A1

    公开(公告)日：2008-01-23

    申请号：EP06425494.9

    申请日：2006-07-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Barlocchi, Gabriele ,  Corona, Pietro ,  Villa, Flavio Francesco

    IPC: H01L21/762

    CPC classification number: H01L21/76264 ,  H01L21/7682

    Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells envisages forming, in a die region (5; 105) of a semiconductor body (2, 17; 102, 117), buried cavities (20, 21, 22; 110', 111', 112') and semiconductor structural elements (13', 14', 15'; 113', 114', 115'), which traverse the buried cavities and are distributed in the die region (5; 105). The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements (13'; 113'), arranged inside a closed region (6; 106), and preventing oxidation of second semiconductor structural elements (14'; 114') outside the closed region (6; 106), so as to form a die buried dielectric layer (29; 129) selectively inside the closed region (6; 106).

    Abstract translation: 半导体本体的;一种用于制造半导体晶片包含SOI绝缘井设想形成，在一个区域（105 5）方法（2，17; 102，117），埋空腔（20，21，22; 110”， 111 '112 '）和半导体结构元件（13'，14' ，15 '; 113'，114'，115' ），其穿过所述掩埋腔和分布在区域（5; 105）。 该方法更超过包括氧化步骤选择性第一相邻的半导体结构元件（13”，113‘），一个封闭的区域（6; 106）内设置的外部，和第二半导体结构元件防止氧化（14’，114' ） 闭区域（6; 106），以便形成一个掩埋介电层，其中（29; 129）选择性地将所述闭合区域（6; 106）的内部。

    Process for manufacturing thick suspended structures of semiconductor material
    10.
    发明公开
    Process for manufacturing thick suspended structures of semiconductor material 有权
    制造厚悬浮结构的方法，由半导体材料制成

    公开(公告)号：EP1770055A1

    公开(公告)日：2007-04-04

    申请号：EP05425676.3

    申请日：2005-09-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Corona, Pietro ,  Villa, Flavio Francesco ,  Barlocchi, Gabriele

    IPC: B81B3/00

    CPC classification number: B81C1/00158 ,  B81B2201/025 ,  B81B2203/0109 ,  B81B2203/0315

    Abstract: A process for manufacturing a suspended structure (20) of semiconductor material envisages the steps of: providing a monolithic body (10) of semiconductor material having a front face (10a); forming a buried cavity (17) within the monolithic body (10), extending at a distance from the front face (10a) and delimiting, with the front face (10a), a surface region (18) of the monolithic body (10), said surface region (18) having a first thickness (w 1 ); carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body (10) towards the surface region (18) and thus form a suspended structure (20) above the buried cavity (17), the suspended structure (20) having a second thickness (w 2 ) greater than the first thickness (w 1 ). The thickening thermal treatment is an annealing treatment.

    Abstract translation: 一种用于制造半导体材料的悬浮结构（20）方法设想的以下步骤：提供半导体材料的整体式主体（10），其具有前表面（10A）; 形成在从所述前表面（10a）的延伸一段距离并限定，与所述整体式主体的前表面（10a）中，表面区域（18）的整体式主体内的掩埋空腔（17）（10）（10） 具有第一厚度（W 1）所述的表面区域（18）; 进行增稠热处理：如，以使整体式主体（10）朝向所述表面区域（18）并且因此半导体材料的迁移形成掩埋空腔（17）之上的悬挂结构（20），所述悬挂结构（ 20）具有第二厚度（W 2）比所述第一厚度更大的（W 1）。 增稠热处理是退火处理。

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