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    A memory device
    2.
    发明公开
    A memory device 有权
    存储设备

    公开(公告)号：EP1306852A2

    公开(公告)日：2003-05-02

    申请号：EP02078984.8

    申请日：2002-09-27

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

    IPC: G11C11/34

    CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

    Abstract: A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

    Abstract translation: 一种存储器件（100），包括多个存储器单元（Mh，k），在半导体材料（203）的芯片中形成的具有第一导电类型的多个绝缘第一区域（220h），至少一个第二区域 在每个第一区域中形成的第二导电类型的第二区域，每个第二区域和对应的第一区域之间的接点限定单向导通入元件（D h，k），用于当正向偏置时选择连接到第二区域的相应存储单元 以及用于接触每个第一区域的至少一个触点（225h） 在每个第一区域中形成多个存取元件，所述存取元件在不插入任何接触的情况下被分组成至少一个由多个相邻存取元件（Dh，k，Dh，k + 1）组成的子集，以及 该存储设备还包括用于同时正向偏置每个子集的访问元件的装置（110c，113,125）。

    A memory device
    3.
    发明公开
    A memory device 有权

    公开(公告)号：EP1306852A3

    公开(公告)日：2004-03-10

    申请号：EP02078984.8

    申请日：2002-09-27

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

    IPC: G11C11/34 ,  G11C16/02

    CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

    Abstract: A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

    Shared address lines for crosspoint memory
    5.
    发明公开
    Shared address lines for crosspoint memory 审中-公开
    Geteilter AdressleitungenfürKreuzpunkt-Speichermatrix

    公开(公告)号：EP1626411A1

    公开(公告)日：2006-02-15

    申请号：EP04425631.1

    申请日：2004-08-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dennison, Charles ,  Lowrey, Tyler

    IPC: G11C11/34 ,  G11C5/02

    CPC classification number: G11C11/22 ,  G11C5/063 ,  G11C11/16 ,  G11C13/0004 ,  G11C2213/79

    Abstract: A crosspoint memory (10) includes a shared address line (12). The shared address line may be coupled to cells (14, 16) above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

    Abstract translation: 交叉点存储器（10）包括共享地址线（12）。 在一个实施例中，共享地址线可以耦合到地址线上方和下方的小区（14,16）。 可以利用电压偏压来选择一个电池，并且取消选择另一个电池。 以这种方式，每个单元可以由相同取向的选择装置和交叉点存储元件组成。 这在一些实施例中可以促进制造和降低成本。

    Dual resistance heater for phase change devices and manufacturing method thereof
    6.
    发明公开
    Dual resistance heater for phase change devices and manufacturing method thereof 审中-公开
    Zweiteiliger WiderstandsheiserfürPhasenwechselspeicher und Herstellungsmethode

    公开(公告)号：EP1677371A1

    公开(公告)日：2006-07-05

    申请号：EP04107070.7

    申请日：2004-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Kim, Yudong ,  Karpov, Ilya V. ,  Kuo, Charles C. ,  Atwood, Greg ,  Marangon, Maria Santina ,  Lowrey, Tyler

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/1683

    Abstract: A dual resistance heater (24) for a phase change material region (28) is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface (26) of the heater material relative to the remainder (27) of the heater material. As a result, the portion (26) of the heater material approximate to the phase change material region (28) is a highly effective heater because of its high resistance, but the bulk (27) of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

    Abstract translation: 通过沉积电阻材料形成用于相变材料区域（28）的双电阻加热器（24）。 然后将加热器材料暴露于植入或等离子体，这增加了加热器材料的表面（26）相对于加热器材料的剩余部分（27）的电阻。 结果，加热器材料的部分（26）由于其高电阻而接近于相变材料区域（28）是高效的加热器，但是加热器材料的体积（27）不是电阻的， 因此，不会增加设备的电压降和当前的使用。

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