Abstract:
A dither matrix is applied to a high-resolution image to compare the value of each of the pixels that compose it with a threshold value of the matrix and to obtain an output value of the matrix (Dither matrix value) from each comparison. To each pixel value (in_value_r) of the image there is applied the algorithm represented by the schematic layout of Figure 7 to obtain the pixel values (Out_r) of a low-resolution image. C 1 -C 5 and n 1 -n 10 are parameters that may be selected by means of predetermined criteria based on comparisons of the low-resolution image, obtained by means of the operations described above, with an equivalent low-resolution image obtained by means of a sample method.
Abstract:
A processing architecture enables execution of one first set of instructions (OsTask1.1, OsTask1.2, ...) and one second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...) compiled for being executed by two different CPUs, the first set of instructions (OsTask1.1, OsTask1.2, ...) not being executable by the second CPU, and the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...) not being executable by the first CPU. The architecture comprises a single CPU (CPU3) configured for executing both the instructions of the first set (OsTask1.1, OsTask1.2, ...) and the instructions of the second set (MmTask2.1, MmTask2.2, MmTask2.3, ...). The single CPU in question (CPU3) being selectively switchable between a first operating mode, in which the single CPU (CPU3) executes the first set instructions (OsTask1.1, OsTask1.2, ...), and a second operating mode, in which the single CPU (CPU3) executes the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3, ...). The single processor (CPU3) is configured for recognizing a switching instruction between the first operating mode and the second operating mode and for switching between the first operating mode and the second operating mode according to the switching instruction. The solution can be generalized to the use of a number of switching instructions between more than two execution modes for different CPUs.
Abstract:
A method of compressing encoding data of a sequence of pictures based on a motion estimation among the successive images in order to remove the temporal redundancy from the data, characterized in that it comprises recognizing a 3:2 pulldown conversion of a series of photograms of a filmed sequence in a sequence of TV frames of number greater than the number of said photograms by duplication of certain pictures in a certain order and eliminating the redundancy due to such picture duplications.
Abstract:
A method of calculating the discrete cosine transform (DCT) of blocks of pixels of a picture includes the steps of defining first subdivision blocks called range blocks, having a fractional and scaleable size N/2 i *N/2 i , where i is an integer number, in respect to a maximum pre-defined size of N*N pixels of blocks of division of said picture, referred to as domain blocks, shiftable by intervals of N / 2 i pixels, and of calculating the DCT on 2 i range blocks of subdivision of a domain block of N*N pixels of said picture, in parallel.
Abstract:
An RGB digital video signal destined to be displayed on a display such as a liquid crystal display (LCD) is converted from the RGB colour space to the YUV colour space. The signal converted into the YUV colour space is subjected to at least a processing operation selected among a sub-sampling operation (24) and a data compression operation (26). The signal is then stored in a memory and the signal read from said memory (12) is then subjected to at least a return operation (28, 30) complementary to the aforesaid processing operation (24, 26). The signal subjected to the aforesaid return operation is lastly reconverted from the YUV colour space to the RGB colour space, thus being susceptible to be displayed on the display.