公开(公告)号：AU628497B2

公开(公告)日：1992-09-17

申请号：AU5202790

申请日：1990-03-20

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT W ,  ALLISON JOHN DAVID ,  MEHTA NIKHIL A ,  DEBACKER KENNETH C ,  JEWETT DOUGLAS E ,  PEET CHARLES E JR ,  CUTTS RICHARD W JR

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00 ,  G06F12/08

Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

公开(公告)号：AT158879T

公开(公告)日：1997-10-15

申请号：AT89122708

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INC

Inventor： CUTTS RICHARD W JR ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN DAVID ,  HORST ROBERT W

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

公开(公告)号：DE68928360D1

公开(公告)日：1997-11-06

申请号：DE68928360

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INC

Inventor： CUTTS RICHARD W ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN DAVID ,  HORST ROBERT W

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

公开(公告)号：DE68928360T2

公开(公告)日：1998-05-07

申请号：DE68928360

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INC

Inventor： CUTTS RICHARD W ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN DAVID ,  HORST ROBERT W

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

公开(公告)号：AU625293B2

公开(公告)日：1992-07-09

申请号：AU5202590

申请日：1990-03-20

Applicant: TANDEM COMPUTERS INC

Inventor： SOUTHWORTH RICHARD A ,  CUTTS RICHARD W ,  HORST ROBERT W ,  ALLISON JOHN DAVID ,  MEHTA NIKHIL A ,  DEBACKER KENNETH C ,  JEWETT DOUGLAS E

IPC: G06F1/12 ,  G06F9/46 ,  G06F11/16

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.