公开(公告)号：CA2003338A1

公开(公告)日：1990-06-09

申请号：CA2003338

申请日：1989-11-20

Applicant: TANDEM COMPUTERS INC

Inventor： CUTTS RICHARD W JR ,  JEWETT DOUGLAS E ,  SOUTHWORTH RICHARD A ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN D ,  HORST ROBERT W

IPC: G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F15/17 ,  G11C29/00 ,  G06F9/30 ,  G06F13/00

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

公开(公告)号：AU625293B2

公开(公告)日：1992-07-09

申请号：AU5202590

申请日：1990-03-20

Applicant: TANDEM COMPUTERS INC

Inventor： SOUTHWORTH RICHARD A ,  CUTTS RICHARD W ,  HORST ROBERT W ,  ALLISON JOHN DAVID ,  MEHTA NIKHIL A ,  DEBACKER KENNETH C ,  JEWETT DOUGLAS E

IPC: G06F1/12 ,  G06F9/46 ,  G06F11/16

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.