公开(公告)号：JPH09146905A

公开(公告)日：1997-06-06

申请号：JP14525096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU JIYOERU WATOSON ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU EFU BURUTSUKAATO ,  UIRIAMU PATAASON BANTON ,  DEIBUITSUDO JIEI GAASHIA ,  ROBAATO DABURIYUU HOOSUTO ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO KINKEIDO

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To obtain a multiplex processor system combining the both of two approaches with a fault telerant architecture, a hardware redundancy and a software recovery technique by a single system. SOLUTION: A multiprocessor system 10 includes a number of sub-processor systems 10A and 10B each of which is substantially composed into the same one. The one CPU 12 is the sub-processor systems 10A and 10B is possible to perform communication through the I/O device 17 of the system of the CPU 12 of the system and a routing element 14. The communication between the I/O device 17 operating in a simplex mode and the CPUs 12 is performed by the message made into a packet. The CPUs 12 and the I/O device are written in the memory of the CPU 12 of the system or are read from the memory. The protection of the memory is maintained by each CPU 12 provided with the propriety inspection for the reading/writing to the memory of the CPU 12.