公开(公告)号：JPH09128356A

公开(公告)日：1997-05-16

申请号：JP14527896

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  DEIBUITSUDO JIEI GAASHIA ,  UIRIAMU PATAASON BANTON ,  UIRIAMU EFU BURUTSUKAATO ,  DANIERU ERU FUAURAA ,  KAATEISU UIIRAADO JIYOONZU JIY ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  FURANKU EI UIRIAMUSU

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To add no delay to access by providing an error inspecting function and performing error inspection by an interface so that no influence is exerted on performance. SOLUTION: A data processing system 10 is equipped with two subprocessor systems 10A and 10B which have substantially the same structure and functions. Each of the subprocessor systems 10A and 10B includes a central processing unit(CPU) 12, a router 14, and plural I/O packet interfaces 16 coupled with many I/O devices 17. The pair of CPUs 12 is each equipped with an interface device. Those interface devices receive specific parts of N-bit data words from the other interface devices to which an error signal detected by miscomparison should be asserted and compare them with specific parts of N-bit data words received from the corresponding CPUs 12.

公开(公告)号：JPH09128349A

公开(公告)日：1997-05-16

申请号：JP14555096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  DEIBUITSUDO JIEI GAASHIA

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To facilitate fault-tolerant operation by providing a network which mutually connects a central processor and an input/output device so that one of central processors gains communication access to one of input/output devices without requesting other's use. SOLUTION: The MPs 18 of subprocessor systems 10A and 10B connect an IEEE1149. one-test bus 17 registers used by the MPs 18 to elements of the subprocessor systems thorugh on-line access port interfaces included in the elements so as to transmit states and control information between the elements and MPs 18. The MPs 18 generate and send message packets to communicate with a CPU 12. The CPU 12, a router 14, and an I/O packet interface 16 are mutually connected by a TNet link L and have a two-way data communication.

公开(公告)号：JPH09244960A

公开(公告)日：1997-09-19

申请号：JP14605796

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  GEARII EFU KIYANBERU ,  RICHIYAADO DABURIYUU KATSUTSU ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  FURANKU EI UIRIAMUSU

IPC: G06F12/14 ,  G06F11/18 ,  G06F15/16 ,  G06F15/163 ,  G06F15/167

Abstract: PROBLEM TO BE SOLVED: To check the error of a processor at an interface spot without affecting the processor performance by providing a specific table means and also a means which receives a message from a peripheral device and decides whether the access should be permitted to a memory means based on the received message. SOLUTION: The routers 14A and 14B are connected to the subprocessor systems 10A and 10B, and the I/O packets 16A and 16B are connected to the routers 14A and 14B respectively. This device of such a constitution has a table means which includes plural entries to discriminate permission of the access to a part of a memory means against one of its peripheral devices. Therefore, the message packet sent via an I/O has the information on the originator and the destination. Then a receiving CPU refers to the external source that is permitted to access its memory via an access propriety check and a conversion (AVT) table and checks whether the access is permitted or not.

公开(公告)号：JPH09134336A

公开(公告)日：1997-05-20

申请号：JP14527096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  RINDA ERIN ZARUZAARA ,  UIRIAMU PATAASON BANTON ,  RICHIYAADO DABURIYUU KATSUTSU ,  DEIBUITSUDO JIEI GAASHIA ,  JIYON SHII KURAUSU ,  SUTEIIBUN JII ROU ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  PATORISHIA ERU HOWAITOSAIDO

IPC: G06F11/18 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  H04L1/24 ,  H04L9/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a single system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: The transmitting clock signals existing on a two-way link are supplied to a pair of transmitting and receiving elements in order to demarcate the clock cycles and also to receive the multi-bit words in a processing system which includes the paired transmitting and receiving elements connected to each other for communication of the multi-bit words including the multi-bit data words and multi-bit command words. Then one of paired transmitting and receiving elements transmits the data to the other element in form of a series of multi-bit data words, transmits the multi-bit data words in every clock cycle and transmits the multi-bit command words in every clock cycle and with no sequence.

公开(公告)号：JPH09146905A

公开(公告)日：1997-06-06

申请号：JP14525096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU JIYOERU WATOSON ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU EFU BURUTSUKAATO ,  UIRIAMU PATAASON BANTON ,  DEIBUITSUDO JIEI GAASHIA ,  ROBAATO DABURIYUU HOOSUTO ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO KINKEIDO

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To obtain a multiplex processor system combining the both of two approaches with a fault telerant architecture, a hardware redundancy and a software recovery technique by a single system. SOLUTION: A multiprocessor system 10 includes a number of sub-processor systems 10A and 10B each of which is substantially composed into the same one. The one CPU 12 is the sub-processor systems 10A and 10B is possible to perform communication through the I/O device 17 of the system of the CPU 12 of the system and a routing element 14. The communication between the I/O device 17 operating in a simplex mode and the CPUs 12 is performed by the message made into a packet. The CPUs 12 and the I/O device are written in the memory of the CPU 12 of the system or are read from the memory. The protection of the memory is maintained by each CPU 12 provided with the propriety inspection for the reading/writing to the memory of the CPU 12.

公开(公告)号：JPH09244906A

公开(公告)日：1997-09-19

申请号：JP14555296

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： JIEFURII AI ISUWANDEII ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  JIYON DEIIN KOODEINTON ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  SUUZAN SUTOON MERADEISU ,  SUTEIIBUN EICHI MIRAA ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  FURANKU EI UIRIAMUSU

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/48 ,  G06F11/18 ,  G06F13/24 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To execute the error check of a processor so as not to affect performance at the spot of an interface. SOLUTION: Routers 14A and 14B are connected to sub processor systems 10A and 10B which are one duplex pair of this multiprocessor system and I/O packet interfaces 16A and 16B are connected to the routers. Message packets are copied by the routers and sent by a method for ensuring the synchronization of the both of the pair. Since interruption issued from an I/O element is provided with the information of the cause of the interruption and transmitted by the message packet similarly to other information transfer, protection by the CRC(cyclic redundancy check) of the interruption is performed and the need of deciding the cause from a CPU side is eliminated. The message packet sent through the I/O is provided with the information of an originator and a destination and a reception CPU refers to an external source for permitting access to the memory by an access propriety check and conversion (AVT) chart and checks whether or not the access is allowed.

公开(公告)号：JPH09134337A

公开(公告)日：1997-05-20

申请号：JP14605596

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： JIYON SHII KURAUSU ,  DEIBUITSUDO JIEI GAASHIA ,  ROBAATO DABURIYUU HOOSUTO ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a single system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: The digital information are communicated among plural processing system elements in the form of a message packet which includes the data to identify these system elements as addresses. Then plural port means of an input/output routing device correspond to the processing system elements and transmit and receive in 2-way fashion the message packet to each other. Furthermore, the routing means answers the address identification data, checks the message packet and sends an error mark to the message packet if an error is detected in order to select one of those port means which are connected together so as to enable a processing system element to send the message packet to another.

公开(公告)号：JPH09128347A

公开(公告)日：1997-05-16

申请号：JP14555196

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  RANDARU JII BANTON ,  JIYON MAIKERU BURAUN ,  UIRIAMU EFU BURUTSUKAATO ,  UIRIAMU PATAASON BANTON ,  GEARII EFU KIYANBERU ,  JIYON DEIIN KOODEINTON ,  RICHIYAADO DABURIYUU KATSUTSU ,  BARII RII DOREKUSURAA ,  HARII FURANKU ERUROTSUDO ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  JIEFURII AI ISUWANDEII ,  DAGURASU YUUJIIN JIYUUITSUTO ,  KAATEISU UIIRAADO JIYOONZU JIY ,  JIEEMUZU SUTEIIBUNSU KURETSUKA ,  JIYON SHII KURAUSU ,  SUTEIIBUN JII ROU ,  SUUZAN SUTOON MERADEISU ,  SUTEIIBUN SHII MEIAAZU ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  PATORISHIA ERU HOWAITOSAIDO ,  FURANKU EI UIRIAMUSU ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G06F11/16 ,  G06F15/16 ,  G06F15/17

Abstract: PROBLEM TO BE SOLVED: To facilitate fault-tolerant operation by including a routing element coupled with the central processor and peripheral device of a subprocessing system so as to transmit data between the central processor and peripheral device of the subprocessing system. SOLUTION: Subprocessor systems 10A and 10B include central processors CPUs 12, routers 14, and plural input/output I/O packet interfaces 16 connected to many I/O devices 17 by characteristic input/output NIO buses. The MPs 18 of the subprocessor system 10A and 10B connect IEEE1149. one-test buses 17 and registers used by the MPs 18 to transmit states and control information between elements and MPs 18 to elements of the subprocessor systems through on-line access port OLAP interfaces included in the elements.

公开(公告)号：JPS6446293A

公开(公告)日：1989-02-20

申请号：JP9332888

申请日：1988-04-15

Applicant: TANDEM COMPUTERS INC

Inventor： DEIBUITSUDO JIEI GAASHIA

IPC: G11C11/401 ,  G01R31/319 ,  G11C29/00 ,  G11C29/14 ,  G11C29/32 ,  G11C29/48

Abstract: PURPOSE: To test a memory system functionally by synchronizing the refresh period of a DRAM with a testing cycle and initially setting the DRAM such that its content is uniquely determined even at pseudo random. CONSTITUTION: A system to be tested by a scanning testing device 10 includes a central processing unit(CPU) 14 connected to a memory system 16 via address and data busses 18 and 20. The memory system 16 includes a support circuit in the form of a memory controller 32 connected to a DRAM array 30 via address, data and control lines 33. The testing device 10 is permitted to access a refresh counter included in the memory controller 32 and including the setting of a refreshing period, the refreshing speed of the DRAM array 30 is synchronized with the starting of a testing mode. Thus, at least the digital system having the memory system including the DRAM is tested functionally.

公开(公告)号：JPS63280340A

公开(公告)日：1988-11-17

申请号：JP9804588

申请日：1988-04-20

Applicant: TANDEM COMPUTERS INC

Inventor： DANIERU II RENOOSUKI ,  DEIBUITSUDO JIEI GAASHIA

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3185