公开(公告)号：JPH02202638A

公开(公告)日：1990-08-10

申请号：JP32246389

申请日：1989-12-11

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  DAGURASU II JIYUUETSUTO ,  RICHIYAADO EE SAUSUWAASU ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To prevent the synchronizing operation from being extremely drifted away by providing an interrupt circuit which responds to the count selected in each of all counters. CONSTITUTION: A cycle counter 71 is so set that it overflows at one point before expiration of a maximum interrupt latency period. An interrupt synchronizing request signal and an interrupt signal are generated by the overflow to force resynchronization. When a processor 40 supplies an interrupt, a code in an interrupt routine forces the occurrence of an event. The synchronizing request signal internally generated in this manner causes resynchronization with the event generated by the interrupt routine.