公开(公告)号：JPH02202637A

公开(公告)日：1990-08-10

申请号：JP32246289

申请日：1989-12-11

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  CHIYAARUZU II PIITO JIYUNIA ,  DAGURASU II JIYUUETSUTO ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To achieve the fault tolerance of high level by swapping pages between a global memory and a local memory at the time of requesting the most frequently used page. CONSTITUTION: Each of CPUs 11 to 13 is provided with a local memory 16, and selected pages are stored in global memories 14 and 15. Pages are swapped between global memories 14 and 15 and the local memory 16 when a request to keep the most frequently used page in the local memory 16 of each CPU is issued.

公开(公告)号：JPH02202638A

公开(公告)日：1990-08-10

申请号：JP32246389

申请日：1989-12-11

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  DAGURASU II JIYUUETSUTO ,  RICHIYAADO EE SAUSUWAASU ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To prevent the synchronizing operation from being extremely drifted away by providing an interrupt circuit which responds to the count selected in each of all counters. CONSTITUTION: A cycle counter 71 is so set that it overflows at one point before expiration of a maximum interrupt latency period. An interrupt synchronizing request signal and an interrupt signal are generated by the overflow to force resynchronization. When a processor 40 supplies an interrupt, a code in an interrupt routine forces the occurrence of an event. The synchronizing request signal internally generated in this manner causes resynchronization with the event generated by the interrupt routine.

公开(公告)号：JPH0713789A

公开(公告)日：1995-01-17

申请号：JP5448394

申请日：1994-02-28

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  CHIYAARUZU II PIITO JIYUNIA ,  DAGURASU II JIYUUETSUTO ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To check the state of each CPU by the other CPU in the case of providing a fault tolerant type computer system. CONSTITUTION: The fault tolerant type computer system is provided with the plural CPU for executing the same instruction stream and a common memory having a memory space to be accessed by all the CPU. Inside the common memory, private memory spaces 155a, 155b and 155c are respectively provided for storing state information for each CPU. Each private memory space enables write only from one CPU corresponding to that space but read is enabled from all the CPU. Thus, it can be immediately and easily evaluated whether the state of its own CPU is equal with the states of the other CPU or not.

公开(公告)号：JPH02202636A

公开(公告)日：1990-08-10

申请号：JP32246189

申请日：1989-12-11

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  RANDARU JII BANTON ,  DAGURASU II JIYUUETSUTO ,  PIITAA SHII NOOUTSUDO ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO TABURIYUU HOOSUTO

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To replace faulty parts without system shutdown by minimizing a porting circuit to separate faulty parts while running the system. CONSTITUTION: When all CPUs 11 to 13 enter the interrupt state, they output the interrupt requests to all memory modules 14 and 15 by individual lines of an interrupt bus 35. When all interrupts are ported, memory modules 14 and 15 transmit the interrupt requests ported to three CPUs 11 to 13 through the bus 35. CPUS 11 to 13 synchronize these ported interrupts with a CPU interrupt signal through an inter-CPU bus 18, and interrupts are indicated to all CPUs 11 to 13 at a common point of an instruction stream.