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公开(公告)号：JPH02202637A
公开(公告)日：1990-08-10
申请号：JP32246289
申请日：1989-12-11
Applicant: TANDEM COMPUTERS INC
Inventor： RICHIYAADO DABURIYUU KATSUTSU , CHIYAARUZU II PIITO JIYUNIA , DAGURASU II JIYUUETSUTO , KENISU SHII DEIBETSUKAA , NIKIIRU EE MEETA , JIYON DEIBITSUDO ARISON , ROBAATO DABURIYUU HOOSUTO
IPC: G06F11/16 , G06F11/00 , G06F11/10 , G06F11/14 , G06F11/18 , G06F11/20 , G06F12/02 , G06F15/16 , G06F15/17 , G11C29/00
Abstract: PURPOSE: To achieve the fault tolerance of high level by swapping pages between a global memory and a local memory at the time of requesting the most frequently used page. CONSTITUTION: Each of CPUs 11 to 13 is provided with a local memory 16, and selected pages are stored in global memories 14 and 15. Pages are swapped between global memories 14 and 15 and the local memory 16 when a request to keep the most frequently used page in the local memory 16 of each CPU is issued.
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公开(公告)号：JPH09244960A
公开(公告)日：1997-09-19
申请号：JP14605796
申请日：1996-06-07
Applicant: TANDEM COMPUTERS INC
Inventor： ROBAATO DABURIYUU HOOSUTO , UIRIAMU EDOWAADO BEIKAA , UIRIAMU PATAASON BANTON , GEARII EFU KIYANBERU , RICHIYAADO DABURIYUU KATSUTSU , DANIERU ERU FUAURAA , DEIBUITSUDO JIEI GAASHIA , POORU ENU HINTEITSUKA , JIEFURII AI ISUWANDEII , DEIBUITSUDO POORU SOONIA , UIRIAMU JIYOERU WATOSON , FURANKU EI UIRIAMUSU
IPC: G06F12/14 , G06F11/18 , G06F15/16 , G06F15/163 , G06F15/167
Abstract: PROBLEM TO BE SOLVED: To check the error of a processor at an interface spot without affecting the processor performance by providing a specific table means and also a means which receives a message from a peripheral device and decides whether the access should be permitted to a memory means based on the received message. SOLUTION: The routers 14A and 14B are connected to the subprocessor systems 10A and 10B, and the I/O packets 16A and 16B are connected to the routers 14A and 14B respectively. This device of such a constitution has a table means which includes plural entries to discriminate permission of the access to a part of a memory means against one of its peripheral devices. Therefore, the message packet sent via an I/O has the information on the originator and the destination. Then a receiving CPU refers to the external source that is permitted to access its memory via an access propriety check and a conversion (AVT) table and checks whether the access is permitted or not.
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Patent Agency Ranking
公开(公告)号：JPH09134336A
公开(公告)日：1997-05-20
申请号：JP14527096
申请日：1996-06-07
Applicant: TANDEM COMPUTERS INC
Inventor： ROBAATO DABURIYUU HOOSUTO , UIRIAMU EDOWAADO BEIKAA , RINDA ERIN ZARUZAARA , UIRIAMU PATAASON BANTON , RICHIYAADO DABURIYUU KATSUTSU , DEIBUITSUDO JIEI GAASHIA , JIYON SHII KURAUSU , SUTEIIBUN JII ROU , DEIBUITSUDO POORU SOONIA , UIRIAMU JIYOERU WATOSON , PATORISHIA ERU HOWAITOSAIDO
Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a single system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: The transmitting clock signals existing on a two-way link are supplied to a pair of transmitting and receiving elements in order to demarcate the clock cycles and also to receive the multi-bit words in a processing system which includes the paired transmitting and receiving elements connected to each other for communication of the multi-bit words including the multi-bit data words and multi-bit command words. Then one of paired transmitting and receiving elements transmits the data to the other element in form of a series of multi-bit data words, transmits the multi-bit data words in every clock cycle and transmits the multi-bit command words in every clock cycle and with no sequence.
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公开(公告)号：JPH0713789A
公开(公告)日：1995-01-17
申请号：JP5448394
申请日：1994-02-28
Applicant: TANDEM COMPUTERS INC
Inventor： RICHIYAADO DABURIYUU KATSUTSU , CHIYAARUZU II PIITO JIYUNIA , DAGURASU II JIYUUETSUTO , KENISU SHII DEIBETSUKAA , NIKIIRU EE MEETA , JIYON DEIBITSUDO ARISON , ROBAATO DABURIYUU HOOSUTO
IPC: G06F11/16 , G06F11/00 , G06F11/10 , G06F11/14 , G06F11/18 , G06F11/20 , G06F12/02 , G06F15/16 , G06F15/17 , G11C29/00
Abstract: PURPOSE: To check the state of each CPU by the other CPU in the case of providing a fault tolerant type computer system. CONSTITUTION: The fault tolerant type computer system is provided with the plural CPU for executing the same instruction stream and a common memory having a memory space to be accessed by all the CPU. Inside the common memory, private memory spaces 155a, 155b and 155c are respectively provided for storing state information for each CPU. Each private memory space enables write only from one CPU corresponding to that space but read is enabled from all the CPU. Thus, it can be immediately and easily evaluated whether the state of its own CPU is equal with the states of the other CPU or not.
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公开(公告)号：JPH02202636A
公开(公告)日：1990-08-10
申请号：JP32246189
申请日：1989-12-11
Applicant: TANDEM COMPUTERS INC
Inventor： RICHIYAADO DABURIYUU KATSUTSU , RANDARU JII BANTON , DAGURASU II JIYUUETSUTO , PIITAA SHII NOOUTSUDO , KENISU SHII DEIBETSUKAA , NIKIIRU EE MEETA , JIYON DEIBITSUDO ARISON , ROBAATO TABURIYUU HOOSUTO
IPC: G06F11/16 , G06F11/00 , G06F11/10 , G06F11/14 , G06F11/18 , G06F11/20 , G06F12/02 , G06F15/16 , G06F15/17 , G11C29/00
Abstract: PURPOSE: To replace faulty parts without system shutdown by minimizing a porting circuit to separate faulty parts while running the system. CONSTITUTION: When all CPUs 11 to 13 enter the interrupt state, they output the interrupt requests to all memory modules 14 and 15 by individual lines of an interrupt bus 35. When all interrupts are ported, memory modules 14 and 15 transmit the interrupt requests ported to three CPUs 11 to 13 through the bus 35. CPUS 11 to 13 synchronize these ported interrupts with a CPU interrupt signal through an inter-CPU bus 18, and interrupts are indicated to all CPUs 11 to 13 at a common point of an instruction stream.
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公开(公告)号：JPH09128347A
公开(公告)日：1997-05-16
申请号：JP14555196
申请日：1996-06-07
Applicant: TANDEM COMPUTERS INC
Inventor： ROBAATO DABURIYUU HOOSUTO , UIRIAMU EDOWAADO BEIKAA , RANDARU JII BANTON , JIYON MAIKERU BURAUN , UIRIAMU EFU BURUTSUKAATO , UIRIAMU PATAASON BANTON , GEARII EFU KIYANBERU , JIYON DEIIN KOODEINTON , RICHIYAADO DABURIYUU KATSUTSU , BARII RII DOREKUSURAA , HARII FURANKU ERUROTSUDO , DANIERU ERU FUAURAA , DEIBUITSUDO JIEI GAASHIA , POORU ENU HINTEITSUKA , JIEFURII AI ISUWANDEII , DAGURASU YUUJIIN JIYUUITSUTO , KAATEISU UIIRAADO JIYOONZU JIY , JIEEMUZU SUTEIIBUNSU KURETSUKA , JIYON SHII KURAUSU , SUTEIIBUN JII ROU , SUUZAN SUTOON MERADEISU , SUTEIIBUN SHII MEIAAZU , DEIBUITSUDO POORU SOONIA , UIRIAMU JIYOERU WATOSON , PATORISHIA ERU HOWAITOSAIDO , FURANKU EI UIRIAMUSU , RINDA ERIN ZARUZAARA
Abstract: PROBLEM TO BE SOLVED: To facilitate fault-tolerant operation by including a routing element coupled with the central processor and peripheral device of a subprocessing system so as to transmit data between the central processor and peripheral device of the subprocessing system. SOLUTION: Subprocessor systems 10A and 10B include central processors CPUs 12, routers 14, and plural input/output I/O packet interfaces 16 connected to many I/O devices 17 by characteristic input/output NIO buses. The MPs 18 of the subprocessor system 10A and 10B connect IEEE1149. one-test buses 17 and registers used by the MPs 18 to transmit states and control information between elements and MPs 18 to elements of the subprocessor systems through on-line access port OLAP interfaces included in the elements.
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公开(公告)号：JPH02202638A
公开(公告)日：1990-08-10
申请号：JP32246389
申请日：1989-12-11
Applicant: TANDEM COMPUTERS INC
Inventor： RICHIYAADO DABURIYUU KATSUTSU , DAGURASU II JIYUUETSUTO , RICHIYAADO EE SAUSUWAASU , KENISU SHII DEIBETSUKAA , NIKIIRU EE MEETA , JIYON DEIBITSUDO ARISON , ROBAATO DABURIYUU HOOSUTO
IPC: G06F9/52 , G06F11/00 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F15/17 , G11C29/00
Abstract: PURPOSE: To prevent the synchronizing operation from being extremely drifted away by providing an interrupt circuit which responds to the count selected in each of all counters. CONSTITUTION: A cycle counter 71 is so set that it overflows at one point before expiration of a maximum interrupt latency period. An interrupt synchronizing request signal and an interrupt signal are generated by the overflow to force resynchronization. When a processor 40 supplies an interrupt, a code in an interrupt routine forces the occurrence of an event. The synchronizing request signal internally generated in this manner causes resynchronization with the event generated by the interrupt routine.
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