公开(公告)号：JP2002313839A

公开(公告)日：2002-10-25

申请号：JP2002057976

申请日：2002-03-04

Applicant: TESSERA INC

Inventor： GRUBE GARY W ,  MATHIEU GAETAN ,  SWEIS JASON ,  GRANGE JOHN

IPC: H01L23/12 ,  B23K20/10 ,  H01L21/60 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor inner lead bonding method in which an operation is not affected by a little size change in a connection element. SOLUTION: The connection element having a lead is arranged on the surface of a chip such that the lead is above a contact 54. The bonding region 62 of each lead is energized down by engaging a bonding tool 60 with the contact 54 of a chip, whereas the first end, that is, base end 38 of the lead is fixed to and held by a dielectric layer structure. This lead is deformed in the shape of a letter S by moving the bonding tool 60 toward the base end, that is, the first end 38 of the lead to urge the bonding region 62 toward the first end 38 and to bend the lead, or the lead is bent down by the tool 60 and then the tool is separated from the lead to be separated from the base end 38 of the lead, and then is moved down so as to fix the lead to the contact 54 of the chip.

公开(公告)号：JP2006013501A

公开(公告)日：2006-01-12

申请号：JP2005181311

申请日：2005-06-21

Applicant: Tessera Inc ,  テセラ,インコーポレイテッド

Inventor： GRUBE GARY W ,  MATHIEU GAETAN ,  SWEIS JASON ,  GRANGE JOHN

IPC: H01L21/60 ,  H01L23/12 ,  B23K20/10 ,  H05K3/34

CPC classification number: H01L24/50 ,  B23K20/10 ,  B23K2201/40 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01082

Abstract: PROBLEM TO BE SOLVED: To provide a method for bonding electrical leads to contacts on semiconductor chips and related components, in the mounting and connection of semiconductor chips. SOLUTION: A bonding region (62) of each lead is urged downward, by engaging a tool (60) with a contact (54) on a chip, while a first or base end (38) of the lead is attached to and held by a dielectric layer structure. The lead is deformed into an S-shaped configuration, by moving the bonding tool (60) horizontally toward the base or first end (38) of the lead, thereby forcing the bonding region (62) toward the first end (38) and bending the lead. Alternatively, the lead is bent downward by the tool, and then the tool is separated from the lead, is shifted away from the base end (38) of the lead, and is further moved downward to secure the lead to the chip contact (54). COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于将半导体芯片的安装和连接中的电引线接合到半导体芯片和相关部件上的触点的方法。 解决方案：通过将工具（60）与芯片上的触点（54）接合在一起，引线的接合区域（62）被向下推动，同时引线的第一或基端（38）附接到 并由介电层结构保持。 通过使接合工具（60）水平地朝向引线的基部或第一端（38）移动，引线变形为S形构造，从而迫使接合区域（62）朝向第一端（38）并弯曲 带头。 或者，引线通过工具向下弯曲，然后工具与引线分离，从引线的基端（38）移开，并进一步向下移动以将引线固定到芯片接触（54 ）。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：AU7369794A

公开(公告)日：1995-02-20

申请号：AU7369794

申请日：1994-07-21

Applicant: TESSERA INC

Inventor： GRUBE GARY W ,  MATHIEW GAETAN ,  SWEIS JASON ,  GRANGE JOHN

IPC: H01L23/12 ,  B23K20/10 ,  H01L21/60 ,  H05K3/34 ,  B23K31/02

Abstract: In a semiconductor inner lead bonding process, a connection component having leads is disposed on the chip surface so that the leads lie above the contacts. A bond region of each lead is forced downwardly by a tool into engagement with a contact on the chip while a first or proximal end of the lead remains attached to a dielectric support structure. The lead is deformed into an S-shaped configuration by moving the bonding tool horizontally towards the proximal or first end of the lead, thereby forcing the bonding region towards the first end and bending or buckling the lead. Alternatively, the lead is bent downwardly by a tool and the tool may then be disengaged from the lead, shifted away from the proximal end of the lead and again advanced downwardly to secure the lead to the chip contact.

公开(公告)号：AU7481194A

公开(公告)日：1995-04-10

申请号：AU7481194

申请日：1994-08-05

Applicant: TESSERA INC

Inventor： SWEIS JASON ,  GILLEO KENNETH BURTON

IPC: H01L23/12 ,  G06K19/077 ,  H01L21/54 ,  H01L23/24 ,  H01R43/00

Abstract: A method for creating an interface between a chip and chip carrier includes spacing the chip a given distance above the chip carrier, and then introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is an elastomer which is hardened into a resilient layer after its introduction into the gap. In another preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and then hardening a liquid between the chip carrier and chip.

公开(公告)号：AU7369194A

公开(公告)日：1995-02-20

申请号：AU7369194

申请日：1994-07-21

Applicant: TESSERA INC

Inventor： DISTEFANO THOMAS H ,  KHANDROS IGOR Y ,  MATHIEW GAETAN ,  SWEIS JASON ,  GRANGE JOHN ,  GRUBE GARY W

IPC: H01L21/60 ,  B23K20/02 ,  B23K20/10 ,  H01L21/00 ,  H01L21/603 ,  H05K3/32

Abstract: A bonding tool for bonding inner leads to semiconductor chips is arranged to capture and align elongated lead sections extending in any one of plural directions, and preferably, in any one of two mutually orthogonal directions. Thus, the tool can be applied to align and bond all of the leads to a chip without turning the tool or the chip even where the leads extend in multiple directions.

公开(公告)号：AU4782293A

公开(公告)日：1994-02-14

申请号：AU4782293

申请日：1993-07-23

Applicant: TESSERA INC

Inventor： DISTEFANO THOMAS H ,  GRUBE GARY W ,  KHANDROS IGOR Y ,  MATHIEW GAETAN ,  SWEIS JASON ,  UNION LAURIE ,  GIBSON DAVID

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18 ,  H05K3/36 ,  H05K3/40

Abstract: A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.

公开(公告)号：EP0674814A4

公开(公告)日：1998-02-25

申请号：EP94924580

申请日：1994-08-05

Applicant: TESSERA INC

Inventor： SWEIS JASON ,  GILLEO KENNETH BURTON

IPC: H01L23/12 ,  G06K19/077 ,  H01L21/54 ,  H01L23/24 ,  H01R43/00

CPC classification number: G06K19/07745 ,  H01L21/54 ,  H01L23/24 ,  H01L2924/0002 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A method for creating an interface between a chip (10) and chip carrier (26) includes spacing the chip (10) a given distance above the chip carrier (26), and then introducing a liquid (50) in the gap (34) between the chip (10) and carrier (26). Preferably, the liquid (50) is an elastomer which is hardened into a resilient layer after its introduction into the gap (34). In another preferred embodiment, the terminals (331-34) on a chip carrier (326) are planarized or otherwise vertically positioned by deforming the terminals (331-34) into set vertical locations with a plate (380), and then hardening a liquid (350) between the chip carrier (326) and chip (310).

Abstract translation: 用于在芯片和芯片载体之间创建接口的方法包括将芯片与芯片载体之间的给定距离间隔开，然后将液体引入芯片和载体之间的间隙中。 优选地，液体是在其引入间隙之后被硬化成弹性层的弹性体。 在另一个优选实施例中，芯片载体上的端子通过使端子变形成具有板的垂直位置，然后使芯片载体和芯片之间的液体硬化而被平坦化或以其它方式垂直定位。