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    1.
    发明专利
    未知

    公开(公告)号：DE10297316T5

    公开(公告)日：2004-12-09

    申请号：DE10297316

    申请日：2002-10-09

    Applicant: TESSERA INC

    Inventor： PFLUGHAUPT L ELLIOTT ,  GIBSON DAVID ,  KIM YOUNG ,  MITCHELL CRAIG S

    IPC: H01L25/18 ,  H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/02 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L31/0336 ,  H01L23/50 ,  G11C5/06

    Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

    Stacked packages
    3.
    发明专利
    Stacked packages 未知

    公开(公告)号：AU2002337834A1

    公开(公告)日：2003-04-22

    申请号：AU2002337834

    申请日：2002-10-09

    Applicant: TESSERA INC

    Inventor： GIBSON DAVID ,  KIM YOUNG ,  PFLUGHAUPT L ELLIOTT ,  MITCHELL CRAIG S

    IPC: H01L25/18 ,  H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/02 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L31/0336

    Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

    Semiconductor connection components and methods with releasable lead support
    5.
    发明专利
    Semiconductor connection components and methods with releasable lead support 未知

    公开(公告)号：AU4782293A

    公开(公告)日：1994-02-14

    申请号：AU4782293

    申请日：1993-07-23

    Applicant: TESSERA INC

    Inventor： DISTEFANO THOMAS H ,  GRUBE GARY W ,  KHANDROS IGOR Y ,  MATHIEW GAETAN ,  SWEIS JASON ,  UNION LAURIE ,  GIBSON DAVID

    IPC: H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18 ,  H05K3/36 ,  H05K3/40

    Abstract: A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.

    MULTI-FREQUENCY NOISE SUPPRESSION CAPACITOR SET
    8.
    发明申请
    MULTI-FREQUENCY NOISE SUPPRESSION CAPACITOR SET 审中-公开
    多频噪声抑制电容器

    公开(公告)号：WO2006009772A3

    公开(公告)日：2007-01-18

    申请号：PCT/US2005021293

    申请日：2005-06-16

    Applicant: TESSERA INC ,  GIBSON DAVID ,  STAVROS ANDY ,  WARNER MICHAEL

    Inventor： GIBSON DAVID ,  STAVROS ANDY ,  WARNER MICHAEL

    IPC: H01R11/16 ,  H01L23/02 ,  H01L23/50 ,  H01L23/64

    CPC classification number: H01L23/66 ,  H01L23/50 ,  H01L23/642 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A decoupling device (10) includes a plurality of capacitors having different capacitances (14, 16, 18) physically mounted in a package (12, 212), and terminals including at least one first terminal (24, 224) and at least one second terminal (26, 226) adapted for mounting the package to a circuit panel. The plural capacitors are connected in parallel between the first and second terminals so as to form plural circuits with different self-resonant frequencies. The device can be mounted as a unit on a circuit board with the first terminals connected to a power conductor and the second terminals connected to a ground conductor, and provides low impedance shunting of noise over a wide frequency spectrum.

    Abstract translation: 解耦装置（10）包括物理地安装在封装（12,212）中的具有不同电容（14,16,18）的多个电容器，以及包括至少一个第一端子（24,224）和至少一个第二端子 端子（26,226），适于将封装安装到电路板。 多个电容器并联连接在第一和第二端子之间，以形成具有不同自谐振频率的多个电路。 该装置可以作为单元安装在电路板上，其中第一端子连接到电源导体，并且第二端子连接到接地导体，并且在宽频谱上提供低阻抗的噪声分流。

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