公开(公告)号：JP2000058637A

公开(公告)日：2000-02-25

申请号：JP29390398

申请日：1998-10-15

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  SO CHIN ,  RO KATETSU

IPC: H01L21/76 ,  H01L21/3205 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To prevent a dishing phenomenon, etc., and to ensure the uniformity of the whole semiconductor substrate by a method wherein an insulating layer is polished preparatorily, the whole substrate is flattened efficiently, and mainly polished by an etch-back process for exposing a masking layer and a shallow trench insulating structure section is formed. SOLUTION: A masking layer 102 is made on the whole surface of the semiconductor substrate 100. The substrate 100 is etched, and shallow trenches 104 are formed. An insulating layer 106 is made on the whole surface of the substrate 100, and the trenches 104 are also filled with the insulating layer. A part of the insulating film 106 covering the masking layer 102 is polished preparatorily, and polished in an extent that the masking layer 102 is not exposed, and an insulating layer 106a is formed. The masking layer 102 is used as an etching stop layer, the insulating film 106a is removed by etching, the masking layer 102 is exposed, the insulating layers are left in the trenches 104, and the insulating layers are used as insulating layers 106b, the surfaces of the insulating layers 106b are flattened, and the insulating layers 106b are formed in shallow trench insulating structure sections.

公开(公告)号：JP2000216374A

公开(公告)日：2000-08-04

申请号：JP961699

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  YO BUNKAN ,  SHU SHIBUN

IPC: H01L29/78 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a MOS transistor. SOLUTION: In this manufacture, a gate oxide layer 202, a polysilicon layer 204, a barrier layer 206, and a conductor layer 208 are made continuously on a substrate. A part of the conductor layer and a part of the barrier layer are removed until the polysilicon layer is exposed, by executing a photolithographic/ etching process. Next, ion implantation is conducted, using a remaining conductor layer 208a and a remaining barrier layer 206a as a mask, so as to form a lightly-doped region 212. A spacer 214 is made on the sidewall of the conductor layer and on the sidewall of the barrier layer. The remaining conductor layer, the polysilicon layer in a position other than the spacer, and the gate oxide layer are removed. The remaining conductor layer and the remaining polysilicon layer constitute a gate having a cross section in the shape of inverted T. A source/drain region which includes a low-doped region is made within the substrate by the ion implantation, using a gate structure as a mask.

公开(公告)号：JPH11186274A

公开(公告)日：1999-07-09

申请号：JP13531598

申请日：1998-05-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YO BUNKAN ,  RIN KENTEI ,  CHIN SHINRAI ,  KO KOSEI

IPC: H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a dual damascene technique which is capable of preventing etching damages and making a change small in critical dimensions. SOLUTION: A first and a second photoresist layer are each previously formed in the prescribed regions of a narrow opening and a wide opening of a dual damascene. A composite layer 37 composed of an HSQ(hydrogen silsesquioxane) layer 34 and an oxide layer 36 provided on the layer 34 is formed surrounding the first and second photoresist layer respectively. After the photoresist layers are removed, the left opening 42 is filled up with an adhesive/barrier layer and a metal layer 40.

公开(公告)号：JP2000323561A

公开(公告)日：2000-11-24

申请号：JP12757299

申请日：1999-05-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YO KOKUJI ,  YEW TRI-RUNG ,  CHIN SHINRAI ,  RO KATETSU

IPC: H01L21/76

Abstract: PROBLEM TO BE SOLVED: To reduce stresses caused by an annealing process by forming a doped silicon dioxide layer on a silicon nitride layer to fill a trench, effecting the annealing process, and removing part of the doped silicon dioxide layer by a planarization step to expose the silicon nitride layer. SOLUTION: A doped silicon dioxide layer 110 is formed on a silicon nitride layer 104 to fill a trench 106. The layer 110 is subjected to an annealing process to be highly densified. The annealing process is performed at about 800-950 deg.C. Part of the layer 110 is removed by, e.g. chemical-mechanical polishing to expose the layer 104. The coefficient of thermal expansion and Young's modulus of the layer 110 are adjusted by adjusting the doping level. This reduces stresses caused during the annealing process, and hence reduces both leaks at contacts and at thresholds or below.

公开(公告)号：JPH11176923A

公开(公告)日：1999-07-02

申请号：JP10136698

申请日：1998-04-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  WU JUAN-YUAN ,  RO KATETSU

IPC: H01L21/76

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a trench isolation part. SOLUTION: A first insulating layer 21 is formed on a semiconductor substrate 20 through a chemical deposition means, and a photoresist layer is formed thereon. The photoresist layer is exposed, developed, and patterned by etching into a trench demarcating mask. Then, a first insulating part 21, a pad oxide layer, and a part of the semiconductor substrate 20 are etched continuously to provide trenches 22a and 22b to the semiconductor substrate 20. The trenches 22a and 22b are set different from each other in width so as to satisfy different needs of semiconductor devices. The trench 22b is wider in width than the trench 22a. The trench demarcating mask is removed. This trench isolation eliminates plate-like recess effect on the substrate, and a semiconductor device is improved in reliability.

公开(公告)号：JP2000216240A

公开(公告)日：2000-08-04

申请号：JP983399

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  RO KATETSU

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To avoid occurrence of an overhang structure at the upper corner part of a contact/via opening, by forming a conformal adhesive/via layer at a contact/via opening formed in a dielectrics layer, and performing an RF sputtering process before forming a conductive layer. SOLUTION: In a dielectrics layer 204 formed on a substrate 200, an opening 206 which exposes a metal structure 202 is formed. In order to cover the opening 206, an adhesive/barrier layer 206 which is conformal to the substrate 200 is formed. Then to remove an overhang structure 208a formed at the upper corner part of the opening 206, an RF sputtering process is performed. In the RF sputtering process, the gas flowing into a reactive chamber is ionized with an RF power source and an ion 209 is accelerated in an electric field. Then a conductive layer 212 is formed. Thus, no overhang structure takes place at the upper corner part of the contact/via opening, with a void removed.

公开(公告)号：JP2000012679A

公开(公告)日：2000-01-14

申请号：JP22164598

申请日：1998-08-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  CHIN SHINRAI

IPC: H01L21/76 ,  H01L21/205 ,  H01L21/306 ,  H01L21/316 ,  H01L21/318

Abstract: PROBLEM TO BE SOLVED: To suppress generation of a fine scratch and a defective part being generated at the top of an oxide plug due to chemical-mechanical polishing by depositing a spin-on glass layer on the chemically and mechanically polished oxide layer and etching back the spin-on glass layer and the oxide layer. SOLUTION: After a linear oxide layer 112 is formed on an exposed substrate surface in a trench, an oxide material is deposited into the trench and at the same time onto the substrate surface, thus forming an oxide layer. The oxide layer is partially eliminated by chemical-mechanical polishing, thus forming an oxide layer 118. Then, a thin spin-on glass layer 122 is deposited on the oxide layer 118, thus covering generated fine scratches and defective parts. Then, the spin-on glass layer 122 is etched back, thus exposing a silicon nitride layer 104, thus eliminating scratches and defective parts another generated on the surface of the oxide layer 118 and at the same time suppressing the another occurrence.

公开(公告)号：JP2000216373A

公开(公告)日：2000-08-04

申请号：JP1231199

申请日：1999-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KENTEI ,  CHIN SHINRAI ,  SHU SHIBUN

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To prevent generation of gate-drain capacitance by implanting ions into a substrate using a second spacer, offset spacer and a gate structure as a mask thereby forming a source/drain region. SOLUTION: An offset spacer 308 having a thickness 311 is formed on the sidewall of a gate structure and first ion implantation processing 312 for implanting ions into a substrate using the gate structure 302 and an offset spacer 308 as a mask is carried out to obtain an LDD(low doping drain) region 314. Subsequently, a second spacer 316 is formed on the outer sidewall of the offset spacer 308 and second ion implantation processing 322 for implanting ions into the substrate 300 using the second spacer 316 and the gate structure 302 as a mask is carried out to form a source-drain region 318 in the LDD region 314.

公开(公告)号：JP2000196079A

公开(公告)日：2000-07-14

申请号：JP37425998

申请日：1998-12-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  RIN KENTEI ,  SHU SHIBUN

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L29/10

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a modified MOS semiconductor suitable for a high level integrated element. SOLUTION: This manufacturing method of a MOS semiconductor includes forming a gate 306 on a substrate 300. The extended source/drain 310a are made on a substrate in the vicinity of the gate. Ion implantation process for implanting heavily impurities which are low in diffusion coefficient within a substrate is carried out. A halogen region which is heavily doped is made under the extended source/drain 310a on the substrate 300. An oblique halogen implantation process is carried out to form a halogen implantation region under the gate, on the side of the extension source/drain region 310a on the substrate 300.

公开(公告)号：JPH11121434A

公开(公告)日：1999-04-30

申请号：JP944998

申请日：1998-01-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHO GIGUN ,  RIN KENTEI ,  CHIN SHINRAI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To provide an etching method which increases etching selectivity between oxide and metal silicide and simplifies the etching process itself. SOLUTION: An etching gas of the same composition and the same flow rate is used for a major etching process wherein an opening 50 is formed on an oxide layer 49 and for an over etching process. The etching gas contains CO. More specifically, the etching gas mixture that contains CHF3 , CF4 , argon and CO is used and the flow rate of each gas is 10-50, 10-50, 100-500 and 100-300 SCCM(standard cubic centimeter per minute).