公开(公告)号：WO2016182609A1

公开(公告)日：2016-11-17

申请号：PCT/US2016/015272

申请日：2016-01-28

Applicant: XILINX, INC.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  ZHANG, Geoffrey

IPC: H04L25/03 ,  H04L27/01

CPC classification number: H04L25/03057 ,  H04L25/03 ,  H04L25/03146 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01 ,  H04L2025/0349 ,  H04L2025/03503

Abstract: In a receiver (100), a decision feedback equalizer (120) provides weighted postcursor decisions (121) to a subtraction block (122) for subtraction from an analog input signal (101) to provide an analog output signal (123). A postcursor decision block (130) compares the analog output signal (123) against positive and negative values (104, 105) of a postcursor coefficient for providing first and second possible decisions (136, 137) for selecting a current postcursor-based decision (116) therebetween responsive to a previous postcursor-based decision (117). A precursor cancellation block (108) receives the analog output signal (123), the previous postcursor-based decision (117) and the current postcursor- based decision (116) for providing a digital output signal (124) for a previous sample of the analog input signal (101). The precursor cancellation block (108) includes comparators (211 -214) for receiving the analog output signal (123) and for respectively receiving threshold inputs (201 -204) different from one another for providing possible digital outputs (215-218) for the analog output signal (123). The selection stage (230) is coupled for receiving the possible digital outputs (215-218) for selection of the digital output signal (124).

Abstract translation: 在接收机（100）中，判决反馈均衡器（120）向减法块（122）提供加权后移判决（121），用于从模拟输入信号（101）减法以提供模拟输出信号（123）。 后端判定块（130）将模拟输出信号（123）与用于提供第一和第二可能判决（136,137）的后移系数的正值和负值（104,105）进行比较，用于选择当前的基于前后的判定（ 116），其响应于先前的基于后移的判定（117）。 前体消除块（108）接收模拟输出信号（123），先前基于后移的判定（117）和当前基于后移的判定（116），用于为先前的样本的数字输出信号（124）提供数字输出信号 模拟输入信号（101）。 前体消除块（108）包括用于接收模拟输出信号（123）和用于分别接收彼此不同的阈值输入（201〜204）的比较器（211-214），用于提供可能的数字输出（215-218） 模拟输出信号（123）。 选择级（230）被耦合用于接收用于选择数字输出信号（124）的可能的数字输出（215-218）。

公开(公告)号：WO2023043509A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/032029

申请日：2022-06-02

Applicant: XILINX, INC.

Inventor： CASEY, Ronan Sean ,  RAJENDRAN, Lokesh ,  CAREY, Declan ,  ZHENG, Kevin ,  HEARNE, Catherine ,  ZHANG, Hongtao

IPC: H04L25/02 ,  G06F13/00 ,  H04L25/49 ,  H04L27/04

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

公开(公告)号：WO2018182869A1

公开(公告)日：2018-10-04

申请号：PCT/US2018/018338

申请日：2018-02-15

Applicant: XILINX, INC.

Inventor： ZHANG, Hongtao ,  FRANS, Yohan ,  ZHANG, Geoffrey

IPC: H03M1/18 ,  H04L25/06 ,  H03M1/36

Abstract: A receiver (100) includes: an automatic gain controller (AGC) (104) configured to receive an analog signal; an analog-to-digital converter (ADC) (106) configured to receive an output from the AGC (104) and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data (111), and a least significant bit of the digitized signal corresponds to an error signal (109); and an adaptation unit (110) configured to control the AGC (104), the ADC (106), or both the AGC (104) and the ADC (106), based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

公开(公告)号：WO2016130360A1

公开(公告)日：2016-08-18

申请号：PCT/US2016/016072

申请日：2016-02-02

Applicant: XILINX, INC.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  ZHANG, Geoffrey ,  CHANG, Kun-Yung

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L2025/03484

Abstract: A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage (308) coupled to receive digital samples (X k ) of an input signal. The first stage generates first decision outputs (â k ) based upon the digital samples. A second stage (310) coupled to receive the digital samples of the input signal. The second stage comprises a filter (350) receiving the first decision outputs (â k ) and generating second decision outputs (output data) based upon the digital samples of the input signal and detected inter-symbol interference (i k ) associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.

Abstract translation: 描述用于滤波集成电路中符号间干扰的电路。 电路包括耦合以接收输入信号的数字采样（Xk）的第一级（308）。 第一阶段基于数字样本产生第一决策输出（âk）。 耦合以接收输入信号的数字样本的第二级（310）。 第二级包括基于输入信号的数字样本和检测到的与第一判定输出相关联的符号间干扰（ik）的接收第一判定输出（â）并产生第二判定输出（输出数据）的滤波器（350） 。 还描述了一种对集成电路中符号间干扰进行滤波的方法。

公开(公告)号：WO2018080652A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/051379

申请日：2017-09-13

Applicant: XILINX, INC.

Inventor： ZHANG, Hongtao ,  WU, Zhaoyin D. ,  BORRELLI, Christopher J. ,  ZHANG, Geoffrey

IPC: G01R31/02 ,  H04L43/02 ,  H04L7/00

Abstract: An example method of performing an eye-scan in a receiver includes: generating (104) digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing (204) the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting (404) the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking (406) the plurality of equalization parameters, suspending (408) phase detection in the clock recovery, offsetting (410) the PI code, collecting (412) an output of the receiver, resuming (414) the phase detection in the clock recovery, and unlocking (414) the equalization parameters to perform the eye scan.

Abstract translation: 在接收器中执行眼睛扫描的示例方法包括：基于采样时钟从输入到接收器的模拟信号生成（104）数字采样，所述采样时钟的相位相移 以基于相位内插器（PI）码的参考时钟; 基于所述接收器的多个均衡参数的第一均衡参数来均衡（204）所述数字样本; 对所述多个均衡参数进行适配（404）并且基于所述数字样本执行时钟恢复以生成所述PI码; （406）所述多个均衡参数，在所述时钟恢复中暂停（408）相位检测，偏移（410）所述PI代码，收集（412）所述接收器的输出，恢复（414） 时钟恢复中的相位检测，以及解锁（414）均衡参数以执行眼部扫描。

公开(公告)号：WO2016190923A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/016872

申请日：2016-02-05

Applicant: XILINX, INC.

Inventor： LIAO, Yu ,  ZHANG, Geoffrey ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  PHAM, Toan ,  WU, Zhaoyin, D.

IPC: H04L25/03

CPC classification number: H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver (100) relates generally to channel adaptation. In this receiver (100), a first signal processing block (101) is coupled to a communications channel (20). The first signal processing block (101) includes: an AGC block (102) and a CTLE block (103) for receiving a modulated signal (21) for providing an analog signal (104); an ADC (105) for converting the analog signal (104) to digital samples (106); and an FFE block (112) for equalizing the digital samples (106) to provide equalized samples (114). A second signal processing block (111) includes: a DFE block (113) for receiving the equalized samples (114) for providing re-equalized samples (116); and a slicer (123) coupled to the DFE block (113) for slicing the re-equalized samples (116). A receiver adaptation block (150) is coupled to the first signal processing block (101) and the second signal processing block (111). The receiver adaptation block (150) is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel (20).

Abstract translation: 接收机（100）一般涉及信道适配。 在该接收机（100）中，第一信号处理块（101）耦合到通信信道（20）。 第一信号处理块（101）包括：AGC块（102）和用于接收用于提供模拟信号（104）的调制信号（21））的CTLE块（103）。 用于将模拟信号（104）转换成数字样本（106）的ADC（105）; 以及用于均衡数字样本（106）以提供均衡样本（114）的FFE块（112）。 第二信号处理块（111）包括：DFE块（113），用于接收用于提供重新均衡的样本（116）的均衡样本（114）; 以及耦合到所述DFE块（113）的限幅器（123），用于对所述重新平衡样本（116）进行切片。 接收机适配块（150）耦合到第一信号处理块（101）和第二信号处理块（111）。 接收机适配块（150）被配置用于提供AGC适配，CTLE适配以及对通信信道（20）的限幅器适配。

公开(公告)号：WO2016168648A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/027825

申请日：2016-04-15

Applicant: XILINX, INC.

Inventor： ZHANG, Hongtao ,  ZHANG, Geoffrey ,  SATARZADEH, Patrick ,  WU, Zhaoyin, D.

IPC: H04L25/06

CPC classification number: H04L27/06 ,  H04L25/061

Abstract: A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver (304) configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit (310) coupled to receive the input signal; and a calibration circuit (308) coupled to the receiver, the calibration circuit having an input (306) for receiving the input signal; an error detection circuit (31 1 ) coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit (340) coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.

Abstract translation: 描述用于在集成电路中接收数据的电路。 所述电路包括被配置为接收输入信号并基于所述输入信号产生输出数据的接收器（304），所述接收机具有耦合以接收所述输入信号的电平检测电路（310） 以及耦合到所述接收器的校准电路（308），所述校准电路具有用于接收所述输入信号的输入（306）; 耦合到所述输入的误差检测电路（31 1），所述误差检测电路被耦合以接收所述输入信号，第一参考电压和第二参考电压; 以及耦合到所述误差检测电路的输出的控制电路（340），其中所述控制电路基于所述输入信号与所述第一参考电压和所述第二参考电压的比较选择性地产生偏移控制信号或幅度控制信号 。 还公开了接收数据的方法。

公开(公告)号：WO2018005137A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/038004

申请日：2017-06-16

Applicant: XILINX, INC.

Inventor： ELZEFTAWI, Mohamed, N. ,  ZHANG, Hongtao

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H03B5/06 ,  H03B5/366 ,  H03B2200/005 ,  H03B2200/0062 ,  H03G3/3036 ,  H04B1/10 ,  H04L25/03885

Abstract: A continuous time linear equalizer comprises an input (311) of a first equalizer path configured to receive a first differential input signal; an input (323) of a second equalizer path configured to receive a second differential input signal; a first programmable load capacitor (312) coupled to an output of the first equalizer path; a second programmable load capacitor (324) coupled to an output of the second equalizer path; and a programmable source capacitor (332) coupled between the first equalizer path and the second equalizer path.

Abstract translation: 连续时间线性均衡器包括被配置为接收第一差分输入信号的第一均衡器路径的输入（311） 第二均衡器路径的输入（323），被配置为接收第二差分输入信号; 耦合到第一均衡器路径的输出的第一可编程负载电容器（312） 耦合到所述第二均衡器路径的输出的第二可编程负载电容器（324） 和耦合在第一均衡器路径和第二均衡器路径之间的可编程源电容器（332）。

公开(公告)号：EP3257208B1

公开(公告)日：2019-07-24

申请号：EP16708501.8

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  ZHANG, Geoffrey ,  CHANG, Kun-Yung

IPC: H04L25/03

公开(公告)号：EP3304835A1

公开(公告)日：2018-04-11

申请号：EP16707299.0

申请日：2016-02-05

Applicant: Xilinx, Inc.

Inventor： LIAO, Yu ,  ZHANG, Geoffrey ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  PHAM, Toan ,  WU, Zhaoyin, D.

IPC: H04L25/03

CPC classification number: H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.