公开(公告)号：WO2016130360A1

公开(公告)日：2016-08-18

申请号：PCT/US2016/016072

申请日：2016-02-02

Applicant: XILINX, INC.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  ZHANG, Geoffrey ,  CHANG, Kun-Yung

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L2025/03484

Abstract: A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage (308) coupled to receive digital samples (X k ) of an input signal. The first stage generates first decision outputs (â k ) based upon the digital samples. A second stage (310) coupled to receive the digital samples of the input signal. The second stage comprises a filter (350) receiving the first decision outputs (â k ) and generating second decision outputs (output data) based upon the digital samples of the input signal and detected inter-symbol interference (i k ) associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.

Abstract translation: 描述用于滤波集成电路中符号间干扰的电路。 电路包括耦合以接收输入信号的数字采样（Xk）的第一级（308）。 第一阶段基于数字样本产生第一决策输出（âk）。 耦合以接收输入信号的数字样本的第二级（310）。 第二级包括基于输入信号的数字样本和检测到的与第一判定输出相关联的符号间干扰（ik）的接收第一判定输出（â）并产生第二判定输出（输出数据）的滤波器（350） 。 还描述了一种对集成电路中符号间干扰进行滤波的方法。

公开(公告)号：WO2017011479A1

公开(公告)日：2017-01-19

申请号：PCT/US2016/041942

申请日：2016-07-12

Applicant: XILINX, INC.

Inventor： KIREEV, Vassili ,  LIAO, Yu

IPC: H03K5/24 ,  H03K19/094 ,  H03K19/177 ,  H04L25/49

CPC classification number: H04L25/4919 ,  H03K5/2481 ,  H03K19/09425 ,  H03K19/17788 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/4917

Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit (302) having a first current path (325) for receiving a first input signal (Dataln) of a pair of differential input signals and a second current path (329) for receiving a second input signal (Dataln_b) of the pair of differential input signals, the transmitter driver circuit comprising a tail current path (327) coupled to each of the first current path and the second current path; a first current source (370) coupled between a first reference voltage (AVCCAUX) and ground (AVSS), wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source (460) coupled between the first reference voltage and a first output node (314) of the transmitter driver circuit; and a second pull-up current source (480) coupled between the first reference voltage and a second output node (320) of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

Abstract translation: 公开了一种用于在集成电路的发射机中产生调制信号的电路。 该电路包括具有用于接收一对差分输入信号的第一输入信号（Dataln）和用于接收第二输入信号（Dataln_b）的第二电流路径（329））的第一电流路径（325）的发射器驱动电路（302） ）所述一对差分输入信号，所述发射器驱动器电路包括耦合到所述第一电流路径和所述第二电流路径中的每一个的尾电流路径（327） 耦合在第一参考电压（AVCCAUX）和地（AVSS）之间的第一电流源（370），其中第一电流源的第一电流与尾电流路径的尾电流成比例; 第一上拉电流源（460），耦合在所述第一参考电压和所述发射器驱动器电路的第一输出节点（314）之间; 以及耦合在所述发射器驱动器电路的所述第一参考电压和第二输出节点（320）之间的第二上拉电流源（480）。 还公开了一种在集成电路的发射机中产生调制信号的方法。

公开(公告)号：WO2016182609A1

公开(公告)日：2016-11-17

申请号：PCT/US2016/015272

申请日：2016-01-28

Applicant: XILINX, INC.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  ZHANG, Geoffrey

IPC: H04L25/03 ,  H04L27/01

CPC classification number: H04L25/03057 ,  H04L25/03 ,  H04L25/03146 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01 ,  H04L2025/0349 ,  H04L2025/03503

Abstract: In a receiver (100), a decision feedback equalizer (120) provides weighted postcursor decisions (121) to a subtraction block (122) for subtraction from an analog input signal (101) to provide an analog output signal (123). A postcursor decision block (130) compares the analog output signal (123) against positive and negative values (104, 105) of a postcursor coefficient for providing first and second possible decisions (136, 137) for selecting a current postcursor-based decision (116) therebetween responsive to a previous postcursor-based decision (117). A precursor cancellation block (108) receives the analog output signal (123), the previous postcursor-based decision (117) and the current postcursor- based decision (116) for providing a digital output signal (124) for a previous sample of the analog input signal (101). The precursor cancellation block (108) includes comparators (211 -214) for receiving the analog output signal (123) and for respectively receiving threshold inputs (201 -204) different from one another for providing possible digital outputs (215-218) for the analog output signal (123). The selection stage (230) is coupled for receiving the possible digital outputs (215-218) for selection of the digital output signal (124).

Abstract translation: 在接收机（100）中，判决反馈均衡器（120）向减法块（122）提供加权后移判决（121），用于从模拟输入信号（101）减法以提供模拟输出信号（123）。 后端判定块（130）将模拟输出信号（123）与用于提供第一和第二可能判决（136,137）的后移系数的正值和负值（104,105）进行比较，用于选择当前的基于前后的判定（ 116），其响应于先前的基于后移的判定（117）。 前体消除块（108）接收模拟输出信号（123），先前基于后移的判定（117）和当前基于后移的判定（116），用于为先前的样本的数字输出信号（124）提供数字输出信号 模拟输入信号（101）。 前体消除块（108）包括用于接收模拟输出信号（123）和用于分别接收彼此不同的阈值输入（201〜204）的比较器（211-214），用于提供可能的数字输出（215-218） 模拟输出信号（123）。 选择级（230）被耦合用于接收用于选择数字输出信号（124）的可能的数字输出（215-218）。

公开(公告)号：WO2016190923A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/016872

申请日：2016-02-05

Applicant: XILINX, INC.

Inventor： LIAO, Yu ,  ZHANG, Geoffrey ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  PHAM, Toan ,  WU, Zhaoyin, D.

IPC: H04L25/03

CPC classification number: H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver (100) relates generally to channel adaptation. In this receiver (100), a first signal processing block (101) is coupled to a communications channel (20). The first signal processing block (101) includes: an AGC block (102) and a CTLE block (103) for receiving a modulated signal (21) for providing an analog signal (104); an ADC (105) for converting the analog signal (104) to digital samples (106); and an FFE block (112) for equalizing the digital samples (106) to provide equalized samples (114). A second signal processing block (111) includes: a DFE block (113) for receiving the equalized samples (114) for providing re-equalized samples (116); and a slicer (123) coupled to the DFE block (113) for slicing the re-equalized samples (116). A receiver adaptation block (150) is coupled to the first signal processing block (101) and the second signal processing block (111). The receiver adaptation block (150) is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel (20).

Abstract translation: 接收机（100）一般涉及信道适配。 在该接收机（100）中，第一信号处理块（101）耦合到通信信道（20）。 第一信号处理块（101）包括：AGC块（102）和用于接收用于提供模拟信号（104）的调制信号（21））的CTLE块（103）。 用于将模拟信号（104）转换成数字样本（106）的ADC（105）; 以及用于均衡数字样本（106）以提供均衡样本（114）的FFE块（112）。 第二信号处理块（111）包括：DFE块（113），用于接收用于提供重新均衡的样本（116）的均衡样本（114）; 以及耦合到所述DFE块（113）的限幅器（123），用于对所述重新平衡样本（116）进行切片。 接收机适配块（150）耦合到第一信号处理块（101）和第二信号处理块（111）。 接收机适配块（150）被配置用于提供AGC适配，CTLE适配以及对通信信道（20）的限幅器适配。

公开(公告)号：EP3257208B1

公开(公告)日：2019-07-24

申请号：EP16708501.8

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  ZHANG, Geoffrey ,  CHANG, Kun-Yung

IPC: H04L25/03

公开(公告)号：EP3304835A1

公开(公告)日：2018-04-11

申请号：EP16707299.0

申请日：2016-02-05

Applicant: Xilinx, Inc.

Inventor： LIAO, Yu ,  ZHANG, Geoffrey ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  PHAM, Toan ,  WU, Zhaoyin, D.

IPC: H04L25/03

CPC classification number: H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.

公开(公告)号：EP3323201A1

公开(公告)日：2018-05-23

申请号：EP16751381.1

申请日：2016-07-12

Applicant: Xilinx, Inc.

Inventor： KIREEV, Vassili ,  LIAO, Yu

IPC: H03K5/24 ,  H03K19/094 ,  H03K19/177 ,  H04L25/49

CPC classification number: H04L25/4919 ,  H03K5/2481 ,  H03K19/09425 ,  H03K19/17788 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/4917

Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

公开(公告)号：EP3295631B1

公开(公告)日：2020-08-19

申请号：EP16703891.8

申请日：2016-01-28

Applicant: Xilinx, Inc.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  ZHANG, Geoffrey

IPC: H04L25/03 ,  H04L27/01

公开(公告)号：EP3257208A1

公开(公告)日：2017-12-20

申请号：EP16708501.8

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： LIAO, Yu ,  ZHANG, Hongtao ,  ZHANG, Geoffrey ,  CHANG, Kun-Yung

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L2025/03484

Abstract: A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage coupled to receive digital samples of an input signal. The first stage generates first decision outputs based upon the digital samples. A second stage is coupled to receive the digital samples of the input signal. The second stage comprises a filter receiving the first decision outputs and generating second decision outputs based upon the digital samples of the input signal and detected inter-symbol interference associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.