公开(公告)号：KR1020080027083A

公开(公告)日：2008-03-26

申请号：KR1020060092537

申请日：2006-09-22

Applicant: 삼성전자주식회사

Inventor： 김연재

IPC: H03M1/12

CPC classification number: H03M1/123 ,  H03M2201/11 ,  H03M2201/17 ,  H03M2201/83

Abstract: An analog to digital converter is provided to decrease the number of pins allocated to an analog input pin by receiving an analog signal by controlling an external channel selector. An analog to digital converter includes a first channel selector(120), an ADC(140), a second channel selector(160), and a memory(180). The first channel selector includes at least one analog channel and at least one analog extension channel and selects one of the channels. The ADC(Analog Digital Converter) converts an analog signal which is applied through the selected channel, to a digital signal. The second channel selector includes at least one digital channel, to which a digital signal is applied, and selects one of the digital channels. The memory includes the same number of registers as the analog channels and the analog extension channels. The memory stores the digital signal on the register corresponding to the selected digital channel.

Abstract translation: 提供模数转换器以通过控制外部通道选择器来接收模拟信号来减少分配给模拟输入引脚的引脚数。 模数转换器包括第一通道选择器（120），ADC（140），第二通道选择器（160）和存储器（180）。 第一通道选择器包括至少一个模拟通道和至少一个模拟扩展通道，并选择一个通道。 ADC（模拟数字转换器）将通过所选通道施加的模拟信号转换为数字信号。 第二信道选择器包括至少一个数字信道，数字信号被施加到该数字信道，并选择一个数字信道。 存储器包括与模拟通道和模拟扩展通道相同数量的寄存器。 存储器将数字信号存储在与选择的数字通道相对应的寄存器上。

公开(公告)号：KR1020080040458A

公开(公告)日：2008-05-08

申请号：KR1020060108450

申请日：2006-11-03

Applicant: 삼성전기주식회사

Inventor： 이영진 ,  김동현

IPC: H03M3/02

CPC classification number: H03M3/39 ,  H03M3/322 ,  H03M2201/62 ,  H03M2201/83

Abstract: A sigma-delta modulator using a multiplier having a logic gate is provided to improve integration of a circuit by forming a corrected value multiplier having a logic gate. A sigma-delta modulator using a multiplier having a logic gate includes a first multiplying unit(110), a signal processing unit(120), a quantization unit(130), a control unit(140), and a corrected value generation unit(150). The first multiplying unit multiplies an input signal by a predetermined coefficient. The signal processing unit reduces a corrected value from an output value of the first multiplying unit, adds the reduced result value to a previous result value, and multiplies the added result value by a predetermined coefficient. The quantization unit quantizes an output signal of the signal processing unit. The control unit transmits a control signal for controlling a generation of the corrected value in response to the output signal of the quantization unit. The corrected value generation unit has a plurality of logic gates which operate in response to the control signal of the control unit. The corrected value generation unit generates the corrected value by multiplying the output signal of the quantization unit by the predetermined coefficient.

Abstract translation: 提供使用具有逻辑门的乘法器的Σ-Δ调制器，以通过形成具有逻辑门的校正值乘法器来改善电路的积分。 使用具有逻辑门的乘法器的Σ-Δ调制器包括第一乘法单元（110），信号处理单元（120），量化单元（130），控制单元（140）和校正值生成单元 150）。 第一乘法单元将输入信号乘以预定系数。 信号处理单元从第一乘法单元的输出值减少校正值，将减小的结果值与先前结果值相加，并将相加结果值乘以预定系数。 量化单元量化信号处理单元的输出信号。 控制单元响应于量化单元的输出信号发送用于控制校正值的产生的控制信号。 校正值生成单元具有响应于控制单元的控制信号而工作的多个逻辑门。 校正值生成单元通过将量化单元的输出信号乘以预定系数来生成校正值。

公开(公告)号：KR1020050081044A

公开(公告)日：2005-08-18

申请号：KR1020040009283

申请日：2004-02-12

Applicant: 매그나칩 반도체 유한회사

Inventor： 오명규

IPC: H03M1/36

CPC classification number: H03M1/0607 ,  H03M1/12 ,  H03M2201/6107 ,  H03M2201/64 ,  H03M2201/83 ,  H03M2201/847

Abstract: 본 발명은 아날로그 디지털 컨버터에 관한 것으로서, 보다 상세하게는 칩 내부의 입력라인에 차지되어 있는 전하를 디스차지 또는 프리차지시켜, 입력라인의 전압과 아날로그 입력전압의 차이에 따른 노이즈 발생을 방지할 수 있도록 하는데 있다.
이를 위해, 본 발명은 복수개의 채널의 아날로그 입력전압을 선택적으로 출력하는 스위칭그룹과, 입력라인의 전위를 상기 아날로그 입력전압과 동전위로 프리차지시키는 프리차지수단과, 상기 프리차지수단에 의해 프리차지된 후에 구동되어 상기 아날로그 입력전압을 전달하는 인에이블수단과, 상기 인에이블수단으로부터 전달된 상기 아날로그 입력전압을 기준전압과 비교 증폭하여 출력하는 비교부를 포함하여 구성함을 특징으로 한다.

公开(公告)号：KR1020120065226A

公开(公告)日：2012-06-20

申请号：KR1020110119910

申请日：2011-11-17

Applicant: 엘지디스플레이 주식회사

Inventor： 강형원

IPC: H03M1/38

CPC classification number: H03M1/462 ,  H03M2201/2291 ,  H03M2201/62 ,  H03M2201/64 ,  H03M2201/83

Abstract: PURPOSE: SAR(Successive Approximation Register) ADC(Analog-Digital Converter) and an analog to digital converting method using the same are provided to maintain an optimized operation speed for resolution by enhancing a response speed of a SAR ADC. CONSTITUTION: A SHA(Sampling/Holding Amplifier)(2) samples and holds an analog voltage inputted from the outside. A comparator(4) outputs a comparison signal according to a comparison result by comparing a level of the held analog voltage and a level of an n bit analog signal. A SAR(Successive Approximation Register) logic circuit(6) successively generates a digital signal from the most significant bit to the least significant bit in response to the comparison signal. A DAC(Digital-Analog Converter)(10) changes the successively outputted digital signal into the n bit analog signal. An output register(8) generates an n bit digital signal by holding digital signals successively outputted from the most significant bit to the least significant bit.

Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模拟数字转换器）和使用其的模数转换方法，以通过提高SAR ADC的响应速度来保持分辨率的优化操作速度。 构成：SHA（取样/保持放大器）（2）采样并保持从外部输入的模拟电压。 比较器（4）通过比较保持的模拟电压的电平和n位模拟信号的电平，根据比较结果输出比较信号。 SAR（连续近似寄存器）逻辑电路（6）响应于比较信号，从最高有效位连续产生数字信号到最低有效位。 DAC（数模转换器）（10）将连续输出的数字信号改变为n位模拟信号。 输出寄存器（8）通过将从最高有效位连续输出的数字信号保持为最低有效位来产生n位数字信号。