Abstract:
Successive two-trip traversals of charges between gates G.sub.0 and G.sub.2 make it possible to obtain beneath gates G.sub.1 and G.sub.2 quantities of charges equal to Q.sub.R, Q.sub.R /2, Q.sub.R /2.sup.2 . . . Q.sub.R /2.sup.i. A readout device for reading charges and connected to gates G.sub.2 and G.sub.4 generates voltages V.sub.R and V.sub.Ri =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i which are compared with a voltage sample V.sub.x to be coded in order to determine by successive approximations the coefficients a.sub.0 . . . a.sub.n which are equal to 0 or to 1 such that V.sub.x =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.n .multidot.V.sub.R /2.sup.n. Depending on the value of a.sub.i, each quantity of charges Q.sub.R /2.sup.i stored beneath gate G.sub.1 is removed beneath diode D.sub.e or stored beneath gate G.sub.3 and then transferred beneath gate G.sub.4.
Abstract:
PURPOSE: A SAR analog to digital converter and conversion method can diminish the switching energy and total capacitor size by offering the sampling value to the bi node of comparator to the respective other equation. CONSTITUTION: It is input the analog input signal and the capacitor array part(100) samples the analog input voltage, the reference voltage and difference voltage of the analog input voltage. The capacitor array part stores the analog input voltage. It is input the analog input voltage and the sampled difference voltage in the respective first input node and the second input shift and the comparison unit compares the analog input voltage and difference voltage.
Abstract:
PURPOSE: A structure and method of circuit design for implementing low power consumption and a minimum area for a flash analog to digital converter are provided to simplify the structure of a convertor for low power consumption by reducing the number of repeated elements. CONSTITUTION: An analog to digital converter(100) includes a FDBD(First maximum bit determination) unit(110) and a SCTH(Signal Conversion to Half Signal) unit(120) The converter comprises a buffer(111), a resistance ladder(130), an amplification and comparison unit(140), an encoder(150), and XNOR(Exclusive NOR) logic unit(160). The FDBD unit outputs a corresponding signal by determining a MSB(Most Significant Bit) value. The SCTHO unit generates an absolute value signal(Vsmall) about the difference between an input analog signal and a 1/2 of a voltage. A whole circuit size and power consumption shrink by reducing the complex elements of the resistance ladder, the amplification and comparison unit, and the encoder.
Abstract:
PURPOSE: A residue amplifier and an analog digital converter using the same are provided to improve dynamic range of input signal under the lowered source voltage condition. CONSTITUTION: A residual voltage amplifier(210) comprises an operational amplifier, and a capacitor circuit. The operational amplifier is connected to a first internal voltage. The capacitor circuit is connected to another input terminal of the operational amplifier. The capacitor circuit includes a first capacitor(C1), a second capacitor(C2), and a third capacitor. The first capacitor is connected to another input terminal of the operational amplifier. The second capacitor is connected to the common terminal of the first capacitor. The third capacitor is connected to the other input terminal of the operational amplifier. The third capacitor is connected to the output terminal of the operational amplifier.
Abstract:
PURPOSE: SAR(Successive Approximation Register) ADC(Analog-Digital Converter) and an analog to digital converting method using the same are provided to maintain an optimized operation speed for resolution by enhancing a response speed of a SAR ADC. CONSTITUTION: A SHA(Sampling/Holding Amplifier)(2) samples and holds an analog voltage inputted from the outside. A comparator(4) outputs a comparison signal according to a comparison result by comparing a level of the held analog voltage and a level of an n bit analog signal. A SAR(Successive Approximation Register) logic circuit(6) successively generates a digital signal from the most significant bit to the least significant bit in response to the comparison signal. A DAC(Digital-Analog Converter)(10) changes the successively outputted digital signal into the n bit analog signal. An output register(8) generates an n bit digital signal by holding digital signals successively outputted from the most significant bit to the least significant bit.
Abstract:
A digital-analog converter and an analog-digital converter using the same are provided to obtain an accurate data conversion result by removing the influence of the parasitic capacitance through a virtual ground. A digital-analog converter(1000) includes a first type capacitor array(320) and a second type capacitor array(340), and a charge re-distributor(360). The first and second type capacitor arrays have the different array configuration. The charge re-distributor resets the charge in response to the digital data set in the first and second type capacitor arrays. The charge re-distributor generates the analog voltage corresponding to the electric charge reset result. The first type capacitor array is a weighted capacitor array. The second type capacitor array is a charge sharing capacitor array.