Charge-transfer coded-voltage generator for use in analog-digital coders
and decoders
    1.
    发明授权
    Charge-transfer coded-voltage generator for use in analog-digital coders and decoders 失效
    电荷传输编码电压发生器,用于模拟数字编码器和解码器

    公开(公告)号:US4350976A

    公开(公告)日:1982-09-21

    申请号:US215134

    申请日:1980-12-10

    Abstract: Successive two-trip traversals of charges between gates G.sub.0 and G.sub.2 make it possible to obtain beneath gates G.sub.1 and G.sub.2 quantities of charges equal to Q.sub.R, Q.sub.R /2, Q.sub.R /2.sup.2 . . . Q.sub.R /2.sup.i. A readout device for reading charges and connected to gates G.sub.2 and G.sub.4 generates voltages V.sub.R and V.sub.Ri =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i which are compared with a voltage sample V.sub.x to be coded in order to determine by successive approximations the coefficients a.sub.0 . . . a.sub.n which are equal to 0 or to 1 such that V.sub.x =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.n .multidot.V.sub.R /2.sup.n. Depending on the value of a.sub.i, each quantity of charges Q.sub.R /2.sup.i stored beneath gate G.sub.1 is removed beneath diode D.sub.e or stored beneath gate G.sub.3 and then transferred beneath gate G.sub.4.

    Abstract translation: 栅极G0和G2之间的电荷的连续两次跳变使得可以获得栅极G1和G2之下的等于QR,QR / 2,QR / 22的电荷量。 。 。 QR / 2i 用于读取电荷并连接到门G2和G4的读出装置产生电压VR和VRi = a0xVR + a1xVR / 2 +。 。 。 + ai-1xVR / 2i-1 + VR / 2i,其与要编码的电压采样Vx进行比较,以便通过逐次逼近来确定系数a0。 。 。 a等于0或1,使得Vx = a0xVR + a1xVR / 2 +。 。 。 + anxVR / 2n。 根据ai的值,存储在栅极G1下方的每个电荷量QR / 2i在二极管De下方被去除或存储在栅极G3下方,然后在栅极G4下方传送。

    SAR 아날로그 디지털 변환기
    2.
    发明公开
    SAR 아날로그 디지털 변환기 失效
    数字近似寄存器模拟到数字转换器和后续逼近寄存器模拟到数字转换方法

    公开(公告)号:KR1020100084746A

    公开(公告)日:2010-07-28

    申请号:KR1020090004052

    申请日:2009-01-19

    Inventor: 유회준 김빈희

    Abstract: PURPOSE: A SAR analog to digital converter and conversion method can diminish the switching energy and total capacitor size by offering the sampling value to the bi node of comparator to the respective other equation. CONSTITUTION: It is input the analog input signal and the capacitor array part(100) samples the analog input voltage, the reference voltage and difference voltage of the analog input voltage. The capacitor array part stores the analog input voltage. It is input the analog input voltage and the sampled difference voltage in the respective first input node and the second input shift and the comparison unit compares the analog input voltage and difference voltage.

    Abstract translation: 目的:SAR模数转换器和转换方法可以通过将比较器的双节点的采样值提供给相应的其他等式来减小开关能量和总电容大小。 构成:输入模拟输入信号,电容阵列部分(100)对模拟输入电压,模拟输入电压的参考电压和差分电压进行采样。 电容器阵列部分存储模拟输入电压。 在相应的第一输入节点和第二输入移位中输入模拟输入电压和采样的差分电压,比较单元比较模拟输入电压和差分电压。

    플래시형 AD 변환기의 저전력화 및 최소 면적의 구현에 관한 회로설계의 구조와 그 방법
    3.
    发明公开
    플래시형 AD 변환기의 저전력화 및 최소 면적의 구현에 관한 회로설계의 구조와 그 방법 有权
    用于实现低功耗和低功率FLASH AD转换器的电路设计及其方法

    公开(公告)号:KR1020120015155A

    公开(公告)日:2012-02-21

    申请号:KR1020100077436

    申请日:2010-08-11

    Applicant: 정태경

    Inventor: 정태경 백승현

    Abstract: PURPOSE: A structure and method of circuit design for implementing low power consumption and a minimum area for a flash analog to digital converter are provided to simplify the structure of a convertor for low power consumption by reducing the number of repeated elements. CONSTITUTION: An analog to digital converter(100) includes a FDBD(First maximum bit determination) unit(110) and a SCTH(Signal Conversion to Half Signal) unit(120) The converter comprises a buffer(111), a resistance ladder(130), an amplification and comparison unit(140), an encoder(150), and XNOR(Exclusive NOR) logic unit(160). The FDBD unit outputs a corresponding signal by determining a MSB(Most Significant Bit) value. The SCTHO unit generates an absolute value signal(Vsmall) about the difference between an input analog signal and a 1/2 of a voltage. A whole circuit size and power consumption shrink by reducing the complex elements of the resistance ladder, the amplification and comparison unit, and the encoder.

    Abstract translation: 目的:提供用于实现低功耗和闪存模数转换器的最小面积的电路设计的结构和方法,以通过减少重复元件的数量来简化用于低功耗的转换器的结构。 构成:模数转换器(100)包括FDBD(第一最大位确定)单元(110)和SCTH(信号转换为半信号)单元(120)。转换器包括缓冲器(111),电阻梯( 130),放大和比较单元(140),编码器(150)和XNOR(异或逻辑)逻辑单元(160)。 FDBD单元通过确定MSB(最高有效位)值来输出相应的信号。 SCTHO单元产生关于输入模拟信号和电压的1/2之间的差的绝对值信号(Vsmall)。 通过减少电阻梯,放大和比较单元以及编码器的复杂元件,可以缩小整个电路尺寸和功耗。

    노이즈-성형 연속 근사 ADC 오버샘플링
    4.
    发明公开
    노이즈-성형 연속 근사 ADC 오버샘플링 审中-实审
    噪声整形逐次逼近ADC过采样

    公开(公告)号:KR1020170091678A

    公开(公告)日:2017-08-09

    申请号:KR1020177017828

    申请日:2015-12-03

    Abstract: 연속근사아날로그-디지털컨버터(ADC)는, 변환사이클시작시입력신호를샘플링및 홀딩하도록배열되는샘플및 홀드디바이스와, 최대유효비트로부터최소유효비트로디지털출력을순차적으로축적하는연속근사레지스터와, 상기연속근사레지스터의출력에기초하여신호를출력하는디지털-아날로그컨버터와, 상기디지털-아날로그컨버터의출력을상기샘플및 홀드디바이스의출력과비교하고, 그출력을상기연속근사레지스터에공급하는비교기와, 변환사이클종료시잔류신호를저장하도록배열되는잔류신호저장디바이스를포함하되, 상기연속근사 ADC는각각의변환사이클시작시상기샘플및 홀드디바이스상에저장되는입력신호에잔류신호저장디바이스로부터의저장된잔류신호를추가하도록배열된다. SAR에의한각각의 ADC 풀변환후, 디지털출력의아날로그변환은해상도가허용하는한 원본입력신호에가능한가깝다. 그러나, SAR의디지털출력의최소유효비트로표현될수 있는값보다작은입력신호의잔류부분이남는다. 정상작동시에, 동일한입력에대한 SAR의일련의출력은동일한디지털값 출력및 동일한잔류값으로나타날것이다. 각각의변환종료시잔류물을저장하고다음의변환의입력신호에잔류물을추가함으로써, 잔류물은시간에따라누적되어출력디지털값에영향을미칠수 있게된다. 다수의변환후, 누적된잔류물이레지스터의최소유효비트로표현되는값보다큰 값까지더하여지고, 디지털값은변환이입력신호단독에대해수행된경우에비해더 높은값일것이다. 이러한방식으로, 잔류신호는출력값의시간에영향을미치고, 따라서, 시간도메인에서디지털출력을처리함으로써고려될수 있다.

    Abstract translation: 逐次逼近模拟 - 数字转换器(ADC),该转换周期开始时,逐次逼近寄存器的至少显著位顺序地累积,从采样和保持装置的数字输出,并且被布置为采样和保持所述输入信号的最显著位,其中 比较器,将数模转换器的输出与采样保持器件的输出进行比较,并将输出提供给逐次逼近寄存器; 包括:被安排用于存储转换周期在残差信号的端部的残留信号存储设备,所述逐次逼近ADC是存储在输入信号中的残留信号的剩余信号存储装置robuteoui到在每个转换周期的开始被存储在采样和保持装置 Lt。 在SAR每次进行ADC拉变换之后,只要分辨率允许,数字输出的模拟转换就尽可能接近原始输入信号。 然而,输入信号的剩余部分仍然小于SAR数字输出的最低有效位可以表示的值。 在正常操作中,相同输入的一系列SAR输出将出现相同的数字值输出和相同的剩余值。 通过在每次转换结束时存储残留物并将残余物添加到下一次转换的输入信号中,残留物可随时间积累以影响输出数字值。 经过多次转换后,积累的残差会累加到一个大于寄存器最低有效位所表示的值的值,并且数字值将比单独对输入信号执行转换时的值更高。 这样,剩余信号影响输出值的时间,因此可以通过在时域中处理数字输出来考虑。

    잔류전압 증폭기 및 이를 이용한 아날로그/디지털 변환기
    5.
    发明公开
    잔류전압 증폭기 및 이를 이용한 아날로그/디지털 변환기 失效
    使用放大器和模拟数字转换器

    公开(公告)号:KR1020090109455A

    公开(公告)日:2009-10-20

    申请号:KR1020080056410

    申请日:2008-06-16

    Abstract: PURPOSE: A residue amplifier and an analog digital converter using the same are provided to improve dynamic range of input signal under the lowered source voltage condition. CONSTITUTION: A residual voltage amplifier(210) comprises an operational amplifier, and a capacitor circuit. The operational amplifier is connected to a first internal voltage. The capacitor circuit is connected to another input terminal of the operational amplifier. The capacitor circuit includes a first capacitor(C1), a second capacitor(C2), and a third capacitor. The first capacitor is connected to another input terminal of the operational amplifier. The second capacitor is connected to the common terminal of the first capacitor. The third capacitor is connected to the other input terminal of the operational amplifier. The third capacitor is connected to the output terminal of the operational amplifier.

    Abstract translation: 目的:提供残留放大器和使用其的模拟数字转换器,以改善在较低的源电压条件下的输入信号的动态范围。 构成:残余电压放大器(210)包括运算放大器和电容器电路。 运算放大器连接到第一内部电压。 电容电路连接到运算放大器的另一输入端。 电容器电路包括第一电容器(C1),第二电容器(C2)和第三电容器。 第一电容器连接到运算放大器的另一个输入端。 第二电容器连接到第一电容器的公共端。 第三个电容连接到运算放大器的另一个输入端。 第三电容器连接到运算放大器的输出端。

    축차 근사 레지스터 아날로그 디지털 변환기 및 그를 이용한 아날로그 디지털 변환방법
    6.
    发明公开
    축차 근사 레지스터 아날로그 디지털 변환기 및 그를 이용한 아날로그 디지털 변환방법 有权
    相继的近似寄存器模拟转换器和模拟转换方法

    公开(公告)号:KR1020120065226A

    公开(公告)日:2012-06-20

    申请号:KR1020110119910

    申请日:2011-11-17

    Inventor: 강형원

    Abstract: PURPOSE: SAR(Successive Approximation Register) ADC(Analog-Digital Converter) and an analog to digital converting method using the same are provided to maintain an optimized operation speed for resolution by enhancing a response speed of a SAR ADC. CONSTITUTION: A SHA(Sampling/Holding Amplifier)(2) samples and holds an analog voltage inputted from the outside. A comparator(4) outputs a comparison signal according to a comparison result by comparing a level of the held analog voltage and a level of an n bit analog signal. A SAR(Successive Approximation Register) logic circuit(6) successively generates a digital signal from the most significant bit to the least significant bit in response to the comparison signal. A DAC(Digital-Analog Converter)(10) changes the successively outputted digital signal into the n bit analog signal. An output register(8) generates an n bit digital signal by holding digital signals successively outputted from the most significant bit to the least significant bit.

    Abstract translation: 目的:提供SAR(逐次逼近寄存器)ADC(模拟数字转换器)和使用其的模数转换方法,以通过提高SAR ADC的响应速度来保持分辨率的优化操作速度。 构成:SHA(取样/保持放大器)(2)采样并保持从外部输入的模拟电压。 比较器(4)通过比较保持的模拟电压的电平和n位模拟信号的电平,根据比较结果输出比较信号。 SAR(连续近似寄存器)逻辑电路(6)响应于比较信号,从最高有效位连续产生数字信号到最低有效位。 DAC(数模转换器)(10)将连续输出的数字信号改变为n位模拟信号。 输出寄存器(8)通过将从最高有效位连续输出的数字信号保持为最低有效位来产生n位数字信号。

    디지털-아날로그 변환기 및 그것을 이용한 아날로그-디지털변환기
    7.
    发明公开
    디지털-아날로그 변환기 및 그것을 이용한 아날로그-디지털변환기 失效
    使用数字模拟转换器和模拟数字转换器

    公开(公告)号:KR1020090022980A

    公开(公告)日:2009-03-04

    申请号:KR1020070098091

    申请日:2007-09-28

    Abstract: A digital-analog converter and an analog-digital converter using the same are provided to obtain an accurate data conversion result by removing the influence of the parasitic capacitance through a virtual ground. A digital-analog converter(1000) includes a first type capacitor array(320) and a second type capacitor array(340), and a charge re-distributor(360). The first and second type capacitor arrays have the different array configuration. The charge re-distributor resets the charge in response to the digital data set in the first and second type capacitor arrays. The charge re-distributor generates the analog voltage corresponding to the electric charge reset result. The first type capacitor array is a weighted capacitor array. The second type capacitor array is a charge sharing capacitor array.

    Abstract translation: 提供数模转换器和使用该数模转换器的模数转换器,以通过去除虚拟接地的寄生电容的影响来获得精确的数据转换结果。 数模转换器(1000)包括第一类型电容器阵列(320)和第二类型电容器阵列(340)和电荷再分配器(360)。 第一和第二类型电容器阵列具有不同的阵列配置。 电荷再分配器响应于第一和第二类型电容器阵列中的数字数据而重置电荷。 充电重新分配器产生对应于电荷复位结果的模拟电压。 第一类电容器阵列是加权电容阵列。 第二类电容器阵列是电荷共享电容阵列。

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