公开(公告)号：US10692842B2

公开(公告)日：2020-06-23

申请号：US16148325

申请日：2018-10-01

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H05K1/18 ,  H01L23/31 ,  G11C5/06 ,  H01L25/075 ,  G06F1/18 ,  H01L23/367 ,  H01L23/538 ,  H01L23/50 ,  H05K1/02 ,  H01L23/36 ,  H01L23/48 ,  H01L23/525 ,  H01L21/56

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

公开(公告)号：US10032752B2

公开(公告)日：2018-07-24

申请号：US15348238

申请日：2016-11-10

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H01L23/48 ,  G11C8/18 ,  H01L23/02

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  G11C8/18 ,  H01L23/02 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

公开(公告)号：US20170256519A1

公开(公告)日：2017-09-07

申请号：US15600050

申请日：2017-05-19

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  H01L23/36

CPC classification number: H01L25/0657 ,  G06F1/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

公开(公告)号：US09679876B2

公开(公告)日：2017-06-13

申请号：US15168789

申请日：2016-05-31

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H05K1/18 ,  G06F1/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/36 ,  H01L23/48 ,  H01L23/525 ,  H01L21/56 ,  H01L23/50 ,  H05K1/02

CPC classification number: H01L25/0657 ,  G06F1/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

公开(公告)号：US20160197058A1

公开(公告)日：2016-07-07

申请号：US15069131

申请日：2016-03-14

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  G11C8/18

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  G11C8/18 ,  H01L23/02 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

公开(公告)号：US09287195B2

公开(公告)日：2016-03-15

申请号：US14186380

申请日：2014-02-21

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L23/48 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  G11C8/18 ,  H01L23/02 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract translation: 微电子组件可以包括与电路板连接的微电子封装。 封装具有微电子元件，其具有背向封装的衬底的前表面，并且通过在前表面上方延伸的导电结构与衬底电连接。 提供在第一和第二并联栅格中或第一和第二单独列中的第一端子可被配置为承载可用于从存储器存储阵列的所有可寻址的存储器位置中确定可寻址存储器位置的地址信息。 第一网格中的第一终端可以具有作为第二网格中的第一终端的信号分配的镜像的信号分配。

公开(公告)号：US09281271B2

公开(公告)日：2016-03-08

申请号：US14187627

申请日：2014-02-24

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L23/50 ,  H01L23/00 ,  H01L25/065 ,  H01L23/12 ,  H01L23/498 ,  G11C5/06

CPC classification number: H01L25/0657 ,  G11C5/063 ,  H01L23/12 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/1715 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract translation: 微电子组件可以包括在其相应的第一和第二表面处具有第一和第二面板触点的电路板，以及每个具有安装到各个面板触点的端子的第一和第二微电子封装。 每个封装可以包括具有面和其上的触点的微电子元件，具有第一和第二表面的基板，以及在第二表面上的端子，用于将封装与外部元件连接。 端子可以包括在第一和第二平行网格内的位置处的第一端子。 第一终端可以被配置为承载可用于封装内的电路的地址信息，以从微电子元件内的存储器存储阵列的所有可寻址的存储器单元中确定可寻址的存储器位置。 第一网格中的第一终端的信号分配可以是第二网格中的第一终端的信号分配的镜像。

公开(公告)号：US09224431B2

公开(公告)日：2015-12-29

申请号：US14199169

申请日：2014-03-06

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: G11C5/02 ,  G11C5/06 ,  H01L25/065 ,  H01L25/10 ,  H01L23/36 ,  H01L23/498 ,  G11C5/04 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L23/13

CPC classification number: G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06165 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

Abstract translation: 微电子结构具有定义存储阵列的活动元件，以及用于接收指定存储阵列内的位置的地址信息的地址输入。 该结构具有第一表面并且可以具有在第一表面处露出的端子。 终端可以包括第一终端，并且该结构可以被配置为将在第一终端接收的地址信息传送到地址输入。 每个第一终端可以具有包括一个或多个地址输入的信号分配。 第一端子设置在与第一表面垂直的理论平面的第一和第二相对侧上，其中设置在第一侧上的第一端子的信号分配是设置在第二端上的第一端子的信号分配的镜像 理论面的一面。

公开(公告)号：US20140328016A1

公开(公告)日：2014-11-06

申请号：US14244060

申请日：2014-04-03

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: G06F1/18

CPC classification number: G06F1/16 ,  G06F1/18 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06156 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic assembly 5 can include first and second microelectronic packages 10a, 10b mounted to respective first and second opposed surfaces 61, 62 of a circuit panel 60. Each microelectronic package 10a, 10b can include a substrate 20 having first and second apertures 26a, 26b extending between first and second surfaces 21, 22 thereof, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface of the substrate and a plurality of contacts 35 exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, and a plurality of terminals 25a exposed at the second surface in a central region 23 thereof. The apertures 26a, 26b of each substrate 20 can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 of each substrate 20 can be disposed between the first and second axes 29a, 29b of the respective substrate 20.

Abstract translation: 微电子组件5可以包括安装到电路板60的相应的第一和第二相对表面61,62的第一和第二微电子封装10a，10b。每个微电子封装10a，10b可以包括具有第一和第二孔26a，26b的衬底20 在其第一和第二表面21,22之间延伸，第一和第二微电子元件30a，30b，其各自具有面向基板的第一表面的表面31和暴露在相应微电子元件的表面处并与之对准的多个触点35 至少一个孔，以及在其中心区域23处在第二表面处暴露的多个端子25a。 每个基板20的孔26a，26b可以具有在相应孔的长度方向上延伸的第一和第二平行轴线29a，29b。 每个基板20的第二表面22的中心区域23可以设置在各个基板20的第一和第二轴线29a，29b之间。

公开(公告)号：US20140328015A1

公开(公告)日：2014-11-06

申请号：US14244007

申请日：2014-04-03

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: G06F1/18

CPC classification number: H01L25/0657 ,  G06F1/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

Abstract translation: 微电子组件（300）或系统（1500）包括至少一个微电子封装（100），所述微电子封装（100）具有面向上安装在衬底（102）的第一表面（108）上方的微电子元件（130），一个或多个柱 ，140）沿着所述微电子元件正面在第一方向（142）延伸的触点（132）。 在基板的第二表面（110）处露出的端子（1057a）的列（104A，105B，107A，107B）沿第一方向延伸。 具有宽度（152）不大于终端列的最小间距（150）的三分之一倍的中心区域（112）的表面（110）处的第一端子（105）可被配置为承载地址 用于确定可寻址存储器位置的信息。 微电子元件的轴向平面可以与中心区域相交。