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    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE
    2.
    发明公开
    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20230252951A1

    公开(公告)日：2023-08-10

    申请号：US18101270

    申请日：2023-01-25

    Applicant: Sharp Display Technology Corporation

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

    IPC: G09G3/36 ,  H01L27/12

    CPC classification number: G09G3/3677 ,  H01L27/124 ,  H01L27/1225 ,  G09G2310/0286 ,  G09G2330/021

    Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal. The semiconductor layer includes a source contact region electrically connected to the first source terminal, a drain contact region electrically connected to the first drain terminal, and a first and a second channel regions separated from each other in a channel length direction between the contact regions when viewed from a normal direction of the substrate. The first gate electrode overlaps the first channel region via an upper gate insulating layer, and the second gate electrode overlaps the second channel region via the upper gate insulating layer.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220406942A1

    公开(公告)日：2022-12-22

    申请号：US17835273

    申请日：2022-06-08

    Applicant: Sharp Display Technology Corporation

    Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA

    IPC: H01L29/786

    Abstract: Each first thin film transistor of a semiconductor device includes: a lower electrode; a first oxide semiconductor layer including a channel region and first and second contact regions; a gate electrode disposed on the channel region with a gate insulating layer interposed therebetween; and a source electrode and a drain electrode connected to the first contact region and the second contact region, respectively. When viewed from a normal direction of the substrate, at least a part of the channel region overlaps the lower electrode, and at least one of the first and second contact regions is located outside the lower electrode. The channel region has a layered structure including a lower layer, an upper layer located between the lower layer and the gate insulating layer, and a high mobility layer disposed between the lower layer and the upper layer and having mobility higher than mobility of the lower layer and the upper layer. In the channel region, the thickness of the upper layer is equal to or less than 1/3 of the thickness of the lower layer, and the thickness of the high mobility layer is equal to or less than 1/2 of the thickness of the lower layer.

    DISPLAY DEVICE
    6.
    发明申请
    DISPLAY DEVICE 有权

    公开(公告)号：US20250149007A1

    公开(公告)日：2025-05-08

    申请号：US18913037

    申请日：2024-10-11

    Applicant: Sharp Display Technology Corporation

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

    IPC: G09G3/36 ,  G06F3/041

    Abstract: A display device includes: a display panel including a HIGH power supply line and a LOW power supply line; and a scan signal line drive circuit including a unit circuit, wherein the unit circuit includes: a SET terminal; a RESET terminal; an output terminal; a first thin film transistor; a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, one of the second source electrode and the second drain electrode being electrically connected to an internal node; and a third thin film transistor, the second gate electrode is an upper gate electrode, another one of the second source electrode and the second drain electrode is electrically connected to the HIGH power supply line, and the second thin film transistor further includes a lower gate electrode.

    TRANSISTOR, CIRCUIT SUBSTRATE, AND DISPLAY DEVICE
    7.
    发明公开
    TRANSISTOR, CIRCUIT SUBSTRATE, AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20240331653A1

    公开(公告)日：2024-10-03

    申请号：US18585148

    申请日：2024-02-23

    Applicant: Sharp Display Technology Corporation

    Inventor： Yohei TAKEUCHI ,  Tatsuya KAWASAKI ,  Kengo HARA ,  Masafumi SUGINO ,  Hajime IMAI ,  Tohru DAITOH

    IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368

    CPC classification number: G09G3/3677 ,  G02F1/136286 ,  G02F1/1368 ,  G09G2310/0286 ,  G09G2310/08

    Abstract: A transistor includes a first electrode, a first semiconductor portion that is at least partly superimposed on the first electrode and that is composed of a semiconductor material, a first insulating film that is interposed between the first electrode and the first semiconductor portion, a second electrode that is superimposed on a part of the first semiconductor portion and that is connected to the first semiconductor portion, and a third electrode that is located in a layer in which the second electrode is located, that is superimposed on a part of the first semiconductor portion, and that is connected to the first semiconductor portion. An electric potential of the second electrode is lower than that of the third electrode. The third electrode includes a first portion that is spaced from the second electrode and a second portion that is spaced from the second electrode opposite the first portion.

    ACTIVE MATRIX SUBSTRATE
    9.
    发明申请
    ACTIVE MATRIX SUBSTRATE 有权

    公开(公告)号：US20230135065A1

    公开(公告)日：2023-05-04

    申请号：US17973790

    申请日：2022-10-26

    Applicant: Sharp Display Technology Corporation

    Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

    IPC: H01L27/12

    Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer. The plurality of oxide semiconductor TFTs include a first TFT including an oxide semiconductor layer extending across the first gate wiring line and the second gate wiring line in the column direction, when viewed from a normal direction of the substrate. Portions of the first gate wiring line and the second gate wiring line, over which the oxide semiconductor layer of the first TFT extends, respectively function as the lower gate electrode and the upper gate electrode of the first TFT. When viewed from the normal direction of the substrate, the first gate wiring line includes a plurality of first notched portions disposed spaced apart from each other and a first solid portion, the first solid portion being a portion other than the plurality of first notch portions. When viewed from the normal direction of the substrate, the second gate wiring line includes a second solid portion including a plurality of first overlapping portions disposed spaced apart from each other, each of the first overlapping portions partially overlapping at least one of the plurality of first notched portions, and a second overlapping portion overlapping the first solid portion. When viewed from the normal direction of the substrate, the second overlapping portion continuously extends from one of two of the plurality of source wiring lines adjacent to each other, to the other of the two source wiring lines adjacent to each other.

    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME
    10.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME 有权

    公开(公告)号：US20230075289A1

    公开(公告)日：2023-03-09

    申请号：US17895226

    申请日：2022-08-25

    Applicant: Sharp Display Technology Corporation

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

    IPC: H01L29/786 ,  H01L29/417 ,  H01L27/32 ,  H01L29/66

    Abstract: An active matrix substrate includes: a first oxide semiconductor layer including a first channel region; a first gate electrode disposed on the substrate side of the first oxide semiconductor layer; a channel protection layer disposed on a side of the first oxide semiconductor layer opposite to the substrate and covering the first channel region; a first TFT having a first source electrode and a first drain electrode in an upper layer of the channel protection layer; a second oxide semiconductor layer; a second gate electrode disposed on a side of the second oxide semiconductor layer opposite to the substrate; and the second TFT having a second source electrode and a second drain electrode disposed on an interlayer insulating layer that covers the second gate electrode, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed of the same layered oxide semiconductor film, the layered oxide semiconductor film has a layered structure including a high mobility oxide semiconductor film and a low mobility oxide semiconductor film disposed on the substrate side of the high mobility oxide semiconductor film and having a lower mobility than a mobility of the high mobility oxide semiconductor film, and the channel protection layer of the first TFT and the gate insulating layer of the second TFT are formed of the same insulating film.

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