公开(公告)号：US20180091128A1

公开(公告)日：2018-03-29

申请号：US15273920

申请日：2016-09-23

Applicant: Altera Corporation

Inventor： Ker Yon Lau

IPC: H03K5/156 ,  H03K19/21

CPC classification number: H03K5/1565 ,  H03K19/21

Abstract: Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals may be swapped, or the sampling clock signals may be swapped, or both may be swapped, at various times. Erroneous samples obtained in one configuration can cancel out other erroneous samples obtained in another configuration.

公开(公告)号：US20180081840A1

公开(公告)日：2018-03-22

申请号：US15268281

申请日：2016-09-16

Applicant: Altera Corporation

Inventor： Evan Custodio

IPC: G06F13/366 ,  G06F13/40 ,  G06F9/44

CPC classification number: G06F13/366 ,  G06F9/4405 ,  G06F13/4022 ,  G06F13/4068 ,  G06F15/7867

Abstract: A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output of the bus switch. The bus switched may be configured to route an incoming packet to a selected one of the two processing nodes in that pipeline stage or may only route the incoming packet to the active node if the other node is undergoing partial reconfiguration. Configured in this way, the hybrid topology supports partial reconfiguration of the processing nodes without disrupting or limiting the operating frequency of the overall network.

公开(公告)号：US09922157B1

公开(公告)日：2018-03-20

申请号：US14802702

申请日：2015-07-17

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Herman Henry Schmit ,  Dana How ,  Mahesh A. Iyer ,  Saurabh Adya

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

公开(公告)号：US09912369B1

公开(公告)日：2018-03-06

申请号：US14962390

申请日：2015-12-08

Applicant: Altera Corporation

Inventor： Michael James Armstrong

IPC: H04B1/40 ,  H04L12/751

CPC classification number: H04B1/40 ,  H04L45/026

Abstract: An integrated circuit for adaptively maintaining a communications link during an idle mode is disclosed. The integrated circuit may operate in a first (active) mode and a second (idle) mode. The integrated circuit includes a transceiver circuit that establishes a communications link with an additional transceiver circuit of an external integrated circuit. The transceiver circuit may receive data packets from the additional transceiver circuit during the first mode. The integrated circuit further includes monitoring circuitry that monitors a health metric associated with maintaining the communications link between the transceiver circuit and the additional transceiver circuit during the second mode. A control circuit may generate keep-alive signals and adaptively adjusts the frequency of the keep-alive signals such that the health metric is satisfied.

公开(公告)号：US09912337B2

公开(公告)日：2018-03-06

申请号：US15400841

申请日：2017-01-06

Applicant: Altera Corporation

Inventor： Woi Jie Hooi ,  Kok Heng Choe

IPC: H03K19/17 ,  G06F21/76 ,  G06F17/50 ,  H03K19/177

CPC classification number: H03K19/1776 ,  G06F17/5054 ,  G06F21/76 ,  H03K19/177 ,  H03K19/17748 ,  H03K19/17756

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

公开(公告)号：US20180052661A1

公开(公告)日：2018-02-22

申请号：US15242923

申请日：2016-08-22

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/487 ,  G06F7/485

CPC classification number: G06F7/4876 ,  G06F7/485 ,  G06F2207/3816 ,  G06F2207/382 ,  G06F2207/483

Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.

公开(公告)号：US09893727B1

公开(公告)日：2018-02-13

申请号：US15389210

申请日：2016-12-22

Applicant: Altera Corporation

Inventor： Sean R. Atsatt ,  Kent Orthner ,  Daniel R. Mansur

IPC: H03K19/0175 ,  H03K19/177

CPC classification number: H03K19/017581 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17748

Abstract: An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.

公开(公告)号：US09893034B2

公开(公告)日：2018-02-13

申请号：US14923187

申请日：2015-10-26

Applicant: Altera Corporation

Inventor： Yuanlin Xie

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: An integrated circuit package may include a first integrated circuit die having a first bump structure, a second integrated circuit die having a second bump structure, and a detachable interconnect structure having first and second conductive structures that is positioned between the first and second integrated circuit dies. In order to establish electrical communication between the first and second integrated circuit dies, the first conductive structure of the detachable interconnect structure is connected to the first bump structure of the first integrated circuit die, and the second conductive structure of the detachable interconnect structure is connected to the second bump structure of the second integrated circuit die. The detachable interconnect structure may also be used to facilitate wafer-level testing prior to packaging the first and second integrated circuit dies to form the integrated circuit package.

公开(公告)号：US09891935B2

公开(公告)日：2018-02-13

申请号：US14825377

申请日：2015-08-13

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Kenneth Chong Yin Tan

IPC: G06F9/445 ,  G06F9/50

CPC classification number: G06F9/44505 ,  G06F9/445 ,  G06F9/5044

Abstract: A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.

公开(公告)号：US20180041201A1

公开(公告)日：2018-02-08

申请号：US15230150

申请日：2016-08-05

Applicant: Altera Corporation

Inventor： Lai Guan Tang ,  Kang Syn Ting

IPC: H03K7/08 ,  H02M1/14 ,  H02M3/00

CPC classification number: H03K7/08 ,  H02M1/14 ,  H02M3/00

Abstract: An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals. The serializer circuit converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.