公开(公告)号：US09262799B2

公开(公告)日：2016-02-16

申请号：US14536477

申请日：2014-11-07

Applicant: Silicon Graphics International Corp.

Inventor： Cheng Liao

IPC: G06F15/80 ,  G06F15/16 ,  G06T1/60 ,  G06F17/16 ,  G06F12/08 ,  G06F9/54

CPC classification number: G06F9/544 ,  G06F9/4887 ,  G06F9/5016 ,  G06F9/5066 ,  G06F12/08 ,  G06F17/16 ,  G06F2212/2542 ,  G06T1/60

Abstract: A method for computing eigenvectors and eigenvalues of a square matrix in a high performance computer involves dynamically reallocating the computer's computing cores for various phases of the computation process.

Abstract translation: 用于计算高性能计算机中的方阵的特征向量和特征值的方法涉及对计算过程的各个阶段动态地重新分配计算机的计算核心。

公开(公告)号：US09237093B2

公开(公告)日：2016-01-12

申请号：US13830432

申请日：2013-03-14

Applicant: Silicon Graphics International Corp.

Inventor： Joseph George Tietz ,  Gregory Michael Thorson ,  Eric C. Fromm

IPC: H04L12/721 ,  H04L12/703 ,  H04L12/803 ,  H04L12/707

CPC classification number: H04L45/28 ,  H04L45/22 ,  H04L45/70 ,  H04L47/122

Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.

Abstract translation: 自适应路由器预测可能的未来拥塞，并且能够在拥塞发生之前选择替代路由，从而避免拥塞。 自适应路由器可以使用主路由，直到它预测将发生拥塞。 自适应路由器在主网络接口上测量数据包流量，如flit volume，以预测拥塞。 自适应路由器在拖尾时间段内保持由主网络接口处理的飞行数量的拖尾和。 如果总和超过阈值，则自适应路由器假定路由将变得拥塞，并且自适应路由器能够考虑在可能的次路由上路由将来的分组，或至少当前分组。

公开(公告)号：US20150278040A1

公开(公告)日：2015-10-01

申请号：US14224795

申请日：2014-03-25

Applicant: Silicon Graphics International Corp.

Inventor： Mark Ronald Sikkink ,  John Francis De Ryckere ,  Joseph Martin Placek ,  Karen Rae Beighley

IPC: G06F11/20 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F11/2007 ,  G06F2201/81 ,  G06F2201/85 ,  H04L1/1848 ,  H04L1/20 ,  H04L1/22 ,  H04L2001/0096

Abstract: A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.

Abstract translation: 系统和方法提供具有多个通道的通信链路，以及带内实时物理层协议，其在故障切换操作期间连续服务，保持所有车道在线，同时消除故障车道。 在物理层接收机处实时监控通道状态，其中链路错误率，每通道错误性能和其他信道度量是已知的。 如果建立通道故障，则与远程端口的单一往返请求/确认协议交换完成故障切换。 如果失败的车道达到可接受的性能水平，则在往返交换期间保持在线，导致不间断的链路服务。 车道可能被带入或不服务，以满足可靠性，可用性和功耗目标。

公开(公告)号：US09128682B2

公开(公告)日：2015-09-08

申请号：US13949920

申请日：2013-07-24

Applicant: Silicon Graphics International Corp.

Inventor： Steven J. Dean ,  Robert E. Mascia ,  Harvey J. Lunsman ,  Michael Kubisiak ,  David R. Collins ,  Timothy S. McCann

IPC: G06F1/20 ,  G06F1/18 ,  H01B7/30 ,  H05K7/20

CPC classification number: G06F1/20 ,  G06F1/181 ,  G06F2200/201 ,  H05K7/20754 ,  H05K7/20827

Abstract: A high performance computing system includes one or more blade enclosures configured to hold a plurality of computing blades, a connection interface, coupled to the one or more blade enclosures, having one or more connectors and a shared power bus that distributes power to the one or more blade enclosures, and at least one power shelf removably coupled to the one or more connectors and configured to hold one or more power supplies. The system may further include the computing blades and the power supplies. The power shelf may include a power distribution board configured to connect the power supplies together on the shared power bus.

Abstract translation: 高性能计算系统包括被配置为保持多个计算刀片的一个或多个刀片外壳，耦合到所述一个或多个刀片外壳的连接接口，其具有一个或多个连接器以及将功率分配给所述一个或多个连接器的共享电源总线 更多的刀片外壳，以及至少一个电源框架，其可移除地联接到所述一个或多个连接器并且被配置为保持一个或多个电源。 该系统还可以包括计算刀片和电源。 电源架可以包括配电板，其配置成在共享电力总线上将电源连接在一起。

公开(公告)号：US09122816B2

公开(公告)日：2015-09-01

申请号：US14542023

申请日：2014-11-14

Applicant: Silicon Graphics International Corp.

Inventor： Thomas Edward McGee

IPC: G06F13/00 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.

Abstract translation: 高性能计算系统提供有ASIC，其根据由另一设备定义的协议与系统中的另一设备进行通信。 ASIC以高速内容可寻址存储器（“CAM”）的形式耦合到可重配置协议表。 CAM包括用于控制由ASIC执行协议的指令。 CAM可以包括在执行协议时遇到意外的信号或其他错误的情况下控制ASIC的指令。 内部ASIC状态数据可以路由到CAM，以允许ASIC在ASIC或其正在通信的设备的设计或制造中产生对错误的合理响应。

公开(公告)号：US20150163954A1

公开(公告)日：2015-06-11

申请号：US14565084

申请日：2014-12-09

Applicant: Silicon Graphics International Corp.

Inventor： Eng Lim Goh ,  John Kichury ,  Lance Evans

IPC: H05K7/14

CPC classification number: H05K7/1498 ,  G06F13/102 ,  H05K7/1487

Abstract: A server is implemented within disk drive device or other drive device. The server-drive device may be used within a server tray having many disk drive devices, along with multiple other server trays in a cabinet of trays. One or more disk drive devices may be implemented in a server tray. The server-drive device may also be used in other applications. By implementing the server within the disk drive, valuable space is saved in a computing device.

Abstract translation: 服务器实现在磁盘驱动器设备或其他驱动设备中。 服务器驱动设备可以在具有许多磁盘驱动器设备的服务器托盘中以及托盘机柜中的多个其他服务器托盘中使用。 可以在服务器托盘中实现一个或多个磁盘驱动器设备。 服务器驱动设备也可以用在其他应用中。 通过在磁盘驱动器内部实现服务器，将有价值的空间保存在计算设备中。

公开(公告)号：US20150146354A1

公开(公告)日：2015-05-28

申请号：US14550444

申请日：2014-11-21

Applicant: Silicon Graphics International Corp.

Inventor： Perry Dennis Franz

IPC: H05K7/14 ,  H05K7/18 ,  H05K5/02

CPC classification number: H05K7/1488 ,  Y10T29/49826

Abstract: A computer server rack has a platform, configured to support at least one server, with a front end and an opposed back end. The server rack also has a height adjuster coupled to the platform, and a control positioned a first distance from the front end and a second distance from the back end. The first distance is smaller than the second distance, and the control is configured to control the height adjuster to change a height of the back end of the platform.

Abstract translation: 计算机服务器机架具有被配置为支持至少一个服务器的平台，其具有前端和相对的后端。 服务器机架还具有联接到平台的高度调节器，以及位于距前端第一距离和与后端距离第二距离的控制器。 第一距离小于第二距离，并且控制构造成控制高度调节器以改变平台后端的高度。

公开(公告)号：US20150130825A1

公开(公告)日：2015-05-14

申请号：US14536477

申请日：2014-11-07

Applicant: Silicon Graphics International Corp.

Inventor： Cheng Liao

IPC: G06T1/60

CPC classification number: G06F9/544 ,  G06F9/4887 ,  G06F9/5016 ,  G06F9/5066 ,  G06F12/08 ,  G06F17/16 ,  G06F2212/2542 ,  G06T1/60

Abstract: A method for computing eigenvectors and eigenvalues of a square matrix in a high performance computer involves dynamically reallocating the computer's computing cores for various phases of the computation process.

Abstract translation: 用于计算高性能计算机中的方阵的特征向量和特征值的方法涉及对计算过程的各个阶段动态地重新分配计算机的计算核心。

公开(公告)号：US20150056867A1

公开(公告)日：2015-02-26

申请号：US14529050

申请日：2014-10-30

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Peter Siltex Yuen

IPC: H01R24/60 ,  H01R13/6599 ,  H01R13/6581

CPC classification number: H01R24/60 ,  H01R13/502 ,  H01R13/6581 ,  H01R13/6599 ,  H01R13/6658 ,  H01R23/7073 ,  H01R24/64 ,  H01R24/68

Abstract: In an embodiment, a micro ethernet connector includes an outer housing that has a recessed front end and a back end. The micro ethernet connector further includes an inner housing that is disposed within the recessed front end of the outer housing. The inner housing has an exposed end. The exposed end includes a recessed channel. The volume of the recessed channel is substantially equal to the volume of a correspondingly shaped protruding printed circuit board of a male micro ethernet connector. A plurality of spring-biased connectors are disposed within the recessed channel of the inner housing.

Abstract translation: 在一个实施例中，微型以太网连接器包括具有凹入的前端和后端的外壳。 微以太网连接器还包括设置在外壳的凹入前端内的内壳。 内壳具有暴露端。 暴露端包括凹陷通道。 凹槽的体积基本上等于雄性微型以太网连接器的相应形状的突出印刷电路板的体积。 多个弹簧偏置连接器设置在内壳体的凹槽内。

公开(公告)号：US20150032921A1

公开(公告)日：2015-01-29

申请号：US14335752

申请日：2014-07-18

Applicant: Silicon Graphics International Corp.

Inventor： Kirill Malkin

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/00 ,  G06F3/0619 ,  G06F3/0649 ,  G06F3/0685

Abstract: The present system enables more efficient I/O processing by providing a mechanism for maintaining data within the locality of reference. One or more accelerator modules may be implemented within a solid state storage device (SSD). The accelerator modules form a caching storage tier that can receive, store and reproduce data. The one or more accelerator modules may place data into the SSD or hard disk drives based on parameters associated with the data.

Abstract translation: 本系统通过提供用于在参考地点内维护数据的机制来实现更有效的I / O处理。 一个或多个加速器模块可以在固态存储设备（SSD）内实现。 加速器模块形成可以接收，存储和再现数据的缓存存储层。 一个或多个加速器模块可以基于与数据相关联的参数将数据放入SSD或硬盘驱动器。