Abstract:
A microelectronic unit includes a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can include a microelectronic element having a bottom surface adjacent the inner surface, a top surface remote from the bottom surface, and a plurality of contacts at the top surface. The microelectronic element can include terminals electrically connected with the contacts of the microelectronic element. The microelectronic unit can include a dielectric region contacting at least the top surface of the microelectronic element. The dielectric region can have a planar surface located coplanar with or above the front surface of the carrier structure. The terminals can be exposed at the surface of the dielectric region for interconnection with an external element.
Abstract:
A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.
Abstract:
A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
Abstract:
A microelectronic assembly including a first and second microelectronic elements. Each of the microelectronic elements have oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element.
Abstract:
A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches. Individual stacked microelectronic units may be separated from the stacked microelectronic assembly by any suitable dicing, sawing or breaking technique.
Abstract:
A microelectronic subassembly 210 includes a substrate 215 having a top surface 216 and at least one peripheral region 219, a microelectronic element 201 mounted over the substrate 215, a plurality of leads 218, 222 electrically connected to the microelectronic element 201 having outer ends overlying the at least one peripheral region 219 of the substrate 215, and vertical conductors 208 electrically connected with the outer ends of the leads. The subassembly includes an encapsulant layer 204 provided over the top surface 216 of the substrate 215 and around the microelectronic element 201 and the vertical conductors 208 for stiffening the substrate 215 at the at least one peripheral region 219 of the substrate for facilitating handling and testing of the subassembly.
Abstract:
A stacked microelectronic assembly is disclosed, as are different embodiments related to the same. The stacked microelectronic assembly includes a plurality of stackable microelectronic units each having a semiconductor element mounted on a substrate, and also includes alignment elements which align and stack the units one atop another. The aligned assembly may be heated to melt or to reflow the conductive bonding material between the units, thereby electrically coupling and bonding corresponding conductive terminals on each unit.
Abstract:
A stacked semiconductor chip assembly is disclosed, as are different embodiments relating to same. The stacked chip assembly preferably includes a plurality of units which include a substrate with microelectronic components mounted on each. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly and uniform spacing. Warping of the stacked package is desirably limited by placing bumpers between adjacent units to provide a balanced support, while applying a downward pressure on the units during reflow to control height tolerances.
Abstract:
A stackable chip assembly is disclosed, as are many different embodiments relating to same. The chip assembly preferably includes at least two substrates with components mounted on each. The substrates are preferably situated with respect to one another such that components on one substrate extend towards the other substrate and vice versa. The components of each substrate preferably extend between each other. In addition various connections between the substrates are disclosed, as well as methods of constructing such chip assemblies.
Abstract:
A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.