公开(公告)号：US20220037352A1

公开(公告)日：2022-02-03

申请号：US17020457

申请日：2020-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

公开(公告)号：US20210375914A1

公开(公告)日：2021-12-02

申请号：US16913677

申请日：2020-06-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L23/522

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a P-type doped semiconductor layer having an N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the P-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the P-type doped semiconductor layer is replaced with a semiconductor plug.

公开(公告)号：US20210320122A1

公开(公告)日：2021-10-14

申请号：US17020383

申请日：2020-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Zhong Zhang ,  Lei Liu ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11526 ,  H01L23/528

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.

公开(公告)号：US20210320094A1

公开(公告)日：2021-10-14

申请号：US16881294

申请日：2020-05-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.

公开(公告)号：US20210272982A1

公开(公告)日：2021-09-02

申请号：US17321258

申请日：2021-05-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jianzhong Wu ,  Kun Zhang ,  Tingting Zhao ,  Rui Su ,  Zhongwang Sun ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/768 ,  H01L27/11556 ,  H01L23/535

Abstract: A method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers above a substrate is formed. A sacrificial plug above and in contact with the channel structure is formed. A slit opening extending vertically through the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first contact portion is formed in the slit opening. The sacrificial plug is removed after forming the first contact portion to expose the channel structure. A channel local contact above and in contact with the channel structure, and a second contact portion above the first contact portion in the slit opening are simultaneously formed.

公开(公告)号：US20210233932A1

公开(公告)日：2021-07-29

申请号：US17228526

申请日：2021-04-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Haojie Song ,  Kun Bao ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11524 ,  H01L23/528 ,  H01L23/535

Abstract: Channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers is formed above a substrate. A local dielectric layer is formed on the dielectric stack. A slit opening extending vertically through the local dielectric layer and the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first source contact portion is formed in the slit opening. A channel local contact opening through the local dielectric layer to expose the channel structure, and a staircase local contact opening through the local dielectric layer to expose one of the conductive layers at a staircase structure on an edge of the memory stack are simultaneously formed. A channel local contact in the channel local contact opening, a second source contact portion above the first source contact portion in the slit opening, and a staircase local contact in the staircase local contact opening are simultaneously formed.

公开(公告)号：US11024641B2

公开(公告)日：2021-06-01

申请号：US16219994

申请日：2018-12-14

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Kun Zhang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a temporary top selective gate cut in an upper portion of the alternating dielectric stack and extending along a lateral direction; forming a plurality of channel holes penetrating the alternating dielectric stack; removing the temporary top selective gate cut; and forming, simultaneously, a plurality of channel structures in the plurality of channel holes and a top selective gate cut structure.

公开(公告)号：US12278209B2

公开(公告)日：2025-04-15

申请号：US17510779

申请日：2021-10-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanwei Shi ,  Yanhong Wang ,  Cheng Gan ,  Liang Chen ,  Wei Liu ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L25/065 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

公开(公告)号：US12262533B2

公开(公告)日：2025-03-25

申请号：US17731524

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Lei Liu ,  Kun Zhang ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/52 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

公开(公告)号：US20240389331A1

公开(公告)日：2024-11-21

申请号：US18792202

申请日：2024-08-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanwei Shi ,  Yanhong Wang ,  Cheng Gan ,  Liang Chen ,  Wei Liu ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H10B43/40 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41

Abstract: In certain aspects, a semiconductor device includes a substrate and a first transistor. The first transistor includes a first well in the substrate and having a recess, a recess gate structure including a protrusion structure, and a first source and a first drain spaced apart by the recess gate structure. The protrusion structure extends into the recess of the first well. The recess gate structure includes a first gate dielectric and a first gate electrode on the first gate dielectric.