公开(公告)号：US20240206181A1

公开(公告)日：2024-06-20

申请号：US18090915

申请日：2022-12-29

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Yuancheng Yang ,  Lei Liu ,  Tao Yang ,  Kun Zhang ,  Dongxue Zhao ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B43/40 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

Abstract: A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.

公开(公告)号：US20230422524A1

公开(公告)日：2023-12-28

申请号：US18196247

申请日：2023-05-11

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Tao Yang ,  Wenxi Zhou ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1441 ,  H01L2924/14511 ,  H01L2924/1431

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first type through stack structures in a first region of a memory stack, an array of second type through stack structures in a second region of the memory stack, a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures, multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures, and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

公开(公告)号：US20230133520A1

公开(公告)日：2023-05-04

申请号：US17539760

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Tao Yang ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  G11C11/22 ,  H01L27/11514 ,  G11C5/10 ,  G11C11/402

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines, and a plurality of slit structures. Each memory cell includes a vertical transistor, and a storage unit coupled to the vertical transistor. The array of memory cells is arranged in rows in a first direction and columns in a second direction. Two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view. Each word line extends in the second direction. Each slit structure extends in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction.

公开(公告)号：US12274049B2

公开(公告)日：2025-04-08

申请号：US17539818

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Tao Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L29/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/78 ,  H10B12/00

Abstract: In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.

公开(公告)号：US20250048646A1

公开(公告)日：2025-02-06

申请号：US18381073

申请日：2023-10-17

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong Zhang ,  Di Wang ,  Dongxue Zhao ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B53/30 ,  H01L29/06 ,  H10B53/20

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stack structure including conductor layers and dielectric layers stacked alternately along a first direction. The semiconductor device may include at least one semiconductor structure penetrating through the stack structure. The semiconductor structure may include a capacitor structure, a first transistor structure, and a second transistor structure extending in the stack structure along the first direction. The second transistor structure, the first transistor structure, and the capacitor structure in a same semiconductor structure may be arranged and connected sequentially along the first direction.

公开(公告)号：US20240206148A1

公开(公告)日：2024-06-20

申请号：US18089472

申请日：2022-12-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L27/10802 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.

公开(公告)号：US20230361031A1

公开(公告)日：2023-11-09

申请号：US17738786

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei LIU ,  Yuancheng Yang ,  Wenxi Zhou ,  Kun Zhang ,  Di Wang ,  Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/528 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L23/5283 ,  H01L27/11551 ,  H01L27/11578

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

公开(公告)号：US20230354579A1

公开(公告)日：2023-11-02

申请号：US17731530

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuancheng YANG ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

公开(公告)号：US20230132574A1

公开(公告)日：2023-05-04

申请号：US17539818

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Tao Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.

公开(公告)号：US12262533B2

公开(公告)日：2025-03-25

申请号：US17731524

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Lei Liu ,  Kun Zhang ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/52 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.