公开(公告)号：US12082408B2

公开(公告)日：2024-09-03

申请号：US17481803

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: H10B41/41 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

公开(公告)号：US12075621B2

公开(公告)日：2024-08-27

申请号：US17459480

申请日：2021-08-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Lei Liu ,  Wenxi Zhou

IPC: H10B43/27 ,  G11C16/04 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H10B43/35

Abstract: A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The drain select gate line is in direct contact with the semiconductor channel, each of the plurality of word lines is in direct contact with the memory film, and the drain select gate line and the plurality of word lines include a same material.

公开(公告)号：US20240206148A1

公开(公告)日：2024-06-20

申请号：US18089472

申请日：2022-12-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L27/10802 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.

公开(公告)号：US20230361031A1

公开(公告)日：2023-11-09

申请号：US17738786

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei LIU ,  Yuancheng Yang ,  Wenxi Zhou ,  Kun Zhang ,  Di Wang ,  Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/528 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L23/5283 ,  H01L27/11551 ,  H01L27/11578

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

公开(公告)号：US20230005864A1

公开(公告)日：2023-01-05

申请号：US17483121

申请日：2021-09-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00 ,  H01L23/532

Abstract: A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. A first semiconductor structure includes a first substrate, and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate, and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

公开(公告)号：US20230005861A1

公开(公告)日：2023-01-05

申请号：US17481838

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanhong Wang ,  Wei Liu ,  Liang Chen ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US20230005858A1

公开(公告)日：2023-01-05

申请号：US17480931

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Liang Chen ,  Wei Liu ,  Yanhong Wang ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.

公开(公告)号：US20230005856A1

公开(公告)日：2023-01-05

申请号：US17480852

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Liang Chen ,  Wei Liu ,  Yanhong Wang ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.

公开(公告)号：US20230005545A1

公开(公告)日：2023-01-05

申请号：US17481902

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanhong Wang ,  Wei Liu ,  Liang Chen ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: G11C16/10 ,  G11C16/04 ,  H01L23/528 ,  G11C16/26 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

公开(公告)号：US20230005542A1

公开(公告)日：2023-01-05

申请号：US17481020

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Wei Liu ,  Zhiliang Xia ,  Liang Chen ,  Yanhong Wang

IPC: G11C16/04 ,  H01L23/528 ,  H01L23/522 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the first semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.