公开(公告)号：US20240206181A1

公开(公告)日：2024-06-20

申请号：US18090915

申请日：2022-12-29

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Yuancheng Yang ,  Lei Liu ,  Tao Yang ,  Kun Zhang ,  Dongxue Zhao ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B43/40 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

Abstract: A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.

公开(公告)号：US20230422524A1

公开(公告)日：2023-12-28

申请号：US18196247

申请日：2023-05-11

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Tao Yang ,  Wenxi Zhou ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1441 ,  H01L2924/14511 ,  H01L2924/1431

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first type through stack structures in a first region of a memory stack, an array of second type through stack structures in a second region of the memory stack, a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures, multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures, and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

公开(公告)号：US20230354599A1

公开(公告)日：2023-11-02

申请号：US17731524

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  Dongxue ZHAO ,  Yuancheng YANG ,  Lei LIU ,  Kun ZHANG ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

公开(公告)号：US20230189516A1

公开(公告)日：2023-06-15

申请号：US17648783

申请日：2022-01-24

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  DongXue Zhao ,  Yuancheng Yang ,  Lei Liu ,  Kun Zhang ,  Di Wang ,  Wenxi Zhou ,  ZhiLiang Xia ,  ZongLiang Huo

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/532

CPC classification number: H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  H01L23/53204

Abstract: The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.

公开(公告)号：US20230142290A1

公开(公告)日：2023-05-11

申请号：US17646549

申请日：2021-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DongXue ZHAO ,  Tao Yang ,  Yuancheng Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  ZongLiang Huo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.

公开(公告)号：US20230133520A1

公开(公告)日：2023-05-04

申请号：US17539760

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Tao Yang ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/108 ,  G11C11/22 ,  H01L27/11514 ,  G11C5/10 ,  G11C11/402

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines, and a plurality of slit structures. Each memory cell includes a vertical transistor, and a storage unit coupled to the vertical transistor. The array of memory cells is arranged in rows in a first direction and columns in a second direction. Two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view. Each word line extends in the second direction. Each slit structure extends in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction.

公开(公告)号：US20230005944A1

公开(公告)日：2023-01-05

申请号：US17747877

申请日：2022-05-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Lei Liu ,  Tao Yang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a stack structure includes interleaved dielectric layers and conductive layers, a channel structure extending in the stack structure, and a doped semiconductor layer arranged on the stack structure. The doped semiconductor layer covers an end of the channel structure and the stack structure, the channel structure includes a channel layer, and the channel layer includes a doped channel layer.

公开(公告)号：US12272645B2

公开(公告)日：2025-04-08

申请号：US17738786

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei Liu ,  Yuancheng Yang ,  Wenxi Zhou ,  Kun Zhang ,  Di Wang ,  Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L23/528 ,  H10B41/20 ,  H10B43/20

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

公开(公告)号：US20250089235A1

公开(公告)日：2025-03-13

申请号：US18374524

申请日：2023-09-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue Zhao ,  Yuancheng Yang ,  Tao Yang ,  Changzhi Sun ,  Wei Liu ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/786

Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises a plurality of vertical transistors, each comprising: a semiconductor layer having a leakage value lower than a pico-ampere and comprising a vertical semiconductor portion and at least one lateral semiconductor portion, a gate dielectric layer comprising a vertical gate dielectric portion on the vertical semiconductor portion and extending in the vertical direction, a gate electrode on the gate dielectric layer and separated from the semiconductor layer by the gate dielectric layer. The disclosed semiconductor device further comprises a plurality of capacitors each coupled with the semiconductor layer of a corresponding one of the plurality of vertical transistors.

公开(公告)号：US20250016985A1

公开(公告)日：2025-01-09

申请号：US18888331

申请日：2024-09-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/66 ,  H01L29/78

Abstract: A memory device includes a vertical transistor including a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The memory device further includes a storage unit coupled to one of the source and the drain, a word line extending in a second direction perpendicular to the first direction, and a body line coupled to the channel portion of the semiconductor body. The word line is between the storage unit and the body line in the first direction.