公开(公告)号：US12107121B2

公开(公告)日：2024-10-01

申请号：US17515563

申请日：2021-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

公开(公告)号：US20240324197A1

公开(公告)日：2024-09-26

申请号：US18306231

申请日：2023-04-24

Applicant: United Microelectronics Corp.

Inventor： Hung Hsun Shuai ,  Chih-Jung Chen

IPC: H10B41/40 ,  H01L23/60 ,  H10B41/30

CPC classification number: H10B41/40 ,  H01L23/60 ,  H10B41/30

Abstract: A semiconductor device includes a substrate, a doped ring, a plurality of contacts, and a plurality of conductive lines. The substrate includes a first region and a second region surrounding the first region. The doped ring is located in the substrate in the second region and surrounds the first region. The doped ring includes a first doped region and a plurality of second doped regions. The first doped region is located in the substrate in the second region and surrounds the first region. The first doped region has an opening. The second doped regions are separated from each other and located in the substrate of the opening. The contacts are electrically connected to the second doped regions. The conductive lines are connected to the contacts and a plurality of conductive layers in the first region.

公开(公告)号：US20240322036A1

公开(公告)日：2024-09-26

申请号：US18736560

申请日：2024-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26533 ,  H01L21/2822 ,  H01L29/0653 ,  H01L29/66681 ,  H01L21/28211

Abstract: A semiconductor device includes a substrate, a buried oxide layer in the substrate and near a surface of the substrate, a gate dielectric layer on the substrate and covering the buried oxide layer, a gate structure disposed on the gate dielectric layer and overlapping the buried oxide layer, a source region and a drift region in the substrate and respectively at two sides of the gate structure, wherein the drift region partially covers a lower edge of the buried oxide layer and exposes a side edge of the buried oxide layer, and a drain region in the drift region.

公开(公告)号：US20240322008A1

公开(公告)日：2024-09-26

申请号：US18731392

申请日：2024-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer, forming a second barrier layer on the first barrier layer, forming a first hard mask on the second barrier layer, removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US20240321993A1

公开(公告)日：2024-09-26

申请号：US18679459

申请日：2024-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

公开(公告)号：US20240319611A1

公开(公告)日：2024-09-26

申请号：US18306995

申请日：2023-04-25

Applicant: United Microelectronics Corp.

Inventor： Zhi Fan Sun ,  Kuo Feng Huang ,  Ming Hsien Chung ,  Hua-Wei Peng ,  Chih Chung Kuo

IPC: G03F7/20 ,  G01F23/14

CPC classification number: G03F7/70341 ,  G01F23/14 ,  G03F7/70525

Abstract: A lithography system includes an immersion lithographic apparatus, a fluid supply device, and a sensor. The fluid supply is configured to supply fluid to the immersion lithographic apparatus. The fluid supply device includes at least one liquid storage tank, an upper liquid pipe and a lower liquid pipe connected to the liquid storage tank. The sensor includes at least one hydraulic pressure gauge. The at least one hydraulic pressure gauge is arranged near a lower part of the liquid storage tank and connected to the lower liquid pipe and the upper liquid pipe so as to measure the hydraulic pressure at a bottom of the liquid storage tank. The height of the liquid level in the liquid storage tank is calculated from the hydraulic pressure.

公开(公告)号：US12100624B2

公开(公告)日：2024-09-24

申请号：US17672638

申请日：2022-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

公开(公告)号：US20240315146A1

公开(公告)日：2024-09-19

申请号：US18674889

申请日：2024-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  H01L27/0248 ,  H10B61/22

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US20240315095A1

公开(公告)日：2024-09-19

申请号：US18135741

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Yi-Feng Hsu

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

公开(公告)号：US20240313074A1

公开(公告)日：2024-09-19

申请号：US18671941

申请日：2024-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4966 ,  H01L29/66681 ,  H01L29/7816

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.