公开(公告)号：US20190102096A1

公开(公告)日：2019-04-04

申请号：US15721493

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Myron Loewen ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0246 ,  G06F2212/1028 ,  G06F2212/654 ,  G06F2212/7201

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine prior state information corresponding to one or more of a power state, a system state, a device state, and an operating system state, and load an indirection structure for a persistent storage media in the background based on the prior state information. Other embodiments are disclosed and claimed.

公开(公告)号：US20190004988A1

公开(公告)日：2019-01-03

申请号：US15635687

申请日：2017-06-28

Applicant: Western Digital Technologies, Inc.

Inventor： Susan Elkington ,  Randy Roberson ,  Randall Hess ,  Michael Stillwell ,  Michael Walker

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F13/4022 ,  G06F12/0246 ,  G06F13/161 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2213/0026 ,  G06F2213/0032

Abstract: Described herein are enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment. In one implementation, a host system is configured to maintain quality of service statistics corresponding to data interactions with a PCIe storage device available via a PCIe switch. The host system may further receive secondary quality of service statistics for one or more other host systems communicatively coupled to the PCIe device via the PCIe switch, and determine a maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain a quality of service for the host systems.

公开(公告)号：US20190004700A1

公开(公告)日：2019-01-03

申请号：US15636496

申请日：2017-06-28

Applicant: Western Digital Technologies, Inc.

Inventor： Hadas Oshinsky ,  Rotem Sela ,  Amir Shaharabany

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A controller addresses portions of non-volatile memory via a memory interface using physical addresses and addresses portions of host data via the host interface using logical addresses. The controller maintains logical to physical mappings and physical to logical mappings for the logical addresses and the physical addresses. The controller is configured to move data from a source logical address to a destination logical address by updating logical to physical mappings and physical address to logical mappings without instructing the non-volatile memory to move the data between physical locations. In one embodiment, this process is used to implement a command to move or defragment data.

公开(公告)号：US20180364924A1

公开(公告)日：2018-12-20

申请号：US16112314

申请日：2018-08-24

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro FUKUTOMI ,  Shingo TANAKA

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A storage system connectable to a host includes a plurality of interface units, a plurality of semiconductor memory modules, each being detachably coupled with one of the interface units, and a controller configured to maintain an address conversion table indicating mappings between logical addresses and physical addresses of memory locations in the semiconductor memory modules. When the controller determines that a first semiconductor memory module needs to be detached, the controller converts physical addresses of the first semiconductor memory module into corresponding logical addresses using the address conversion table and copies valid data stored in the corresponding logical addresses to another semiconductor memory module and update the address conversion table to indicate new mappings for the corresponding logical addresses of the valid data.

公开(公告)号：US20180336125A1

公开(公告)日：2018-11-22

申请号：US16051370

申请日：2018-07-31

Applicant: Western Digital Technologies, Inc.

Inventor： Ajith Kumar Battaje ,  Tanay Goel ,  Sandeep Sharma ,  Saurabh Manchanda ,  Arun Kumar Medapati

IPC: G06F12/02 ,  G06F12/1009 ,  G06F17/30

CPC classification number: G06F12/0246 ,  G06F12/1009 ,  G06F16/9024 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive a read request for a first translation table entry associated with a logical block, identify a dump unit associated with the logical block using a hash function, determine a dump group associated with the dump unit, and identify a second translation table entry associated with the dump unit.

公开(公告)号：US20180314627A1

公开(公告)日：2018-11-01

申请号：US16030232

申请日：2018-07-09

Applicant: Longitude Enterprise Flash S.a.r.l.

Inventor： Evan Orme ,  James G. Peterson ,  Kevin Vigor ,  David Flynn

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/108 ,  G06F12/0246 ,  G06F2003/0694 ,  G06F2211/109 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7208 ,  H04L12/4625 ,  H04L12/6418 ,  H04L12/66 ,  H04L67/1097 ,  H05K7/1444

Abstract: A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit. An index of the data offsets (e.g., second portions of the physical addresses) may be persisted on the storage device. The first portion of the address may be associated with logical addresses of the data in a forward index. The forward index may omit the second portion of the physical addresses, which may reduce the memory overhead of the index and/or allow the forward index to reference larger storage devices. Data of a particular logical address may be accessed using the first portion of the physical address maintained in the forward index, and the second portion of the media address stored on the storage device.

公开(公告)号：US20180285260A1

公开(公告)日：2018-10-04

申请号：US15476866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm

IPC: G06F12/06 ,  G06F12/0873 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/02 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/0638 ,  G06F12/0246 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0891 ,  G06F13/1694 ,  G06F13/4239 ,  G06F2212/7201

Abstract: Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.

公开(公告)号：US20180276114A1

公开(公告)日：2018-09-27

申请号：US15693275

申请日：2017-08-31

Applicant: Toshiba Memory Corporation

Inventor： Sho KODAMA

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0679 ,  G06F12/0638 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/205 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7206

Abstract: A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.

公开(公告)号：US20180275882A1

公开(公告)日：2018-09-27

申请号：US15995945

申请日：2018-06-01

Applicant: Western Digital Technologies, Inc.

Inventor： Sandeep Sharma ,  Saurabh Manchanda

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0605 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0238 ,  G06F12/10 ,  G06F12/1018 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/214 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks; determine a size of the one or more data blocks; determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block; retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure; determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and create an entry for the physical block in the dynamically sized reverse map.

公开(公告)号：US10082961B2

公开(公告)日：2018-09-25

申请号：US14657765

申请日：2015-03-13

Applicant: SK hynix Inc.

Inventor： Sang Bin Park

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/221 ,  G06F2212/7201

Abstract: A memory system includes a first control circuit part configured to communicate with a host through a first host channel, a second control circuit part configured to communicate with the host through a second host channel, a first chip group configured to communicate with the first control circuit part through a first internal channel, and a second chip group configured to communicate with the second control circuit part through a second internal channel, wherein the first control circuit part and the second control circuit part alternately receive a plurality of data inputted through one of the first and second host channels, which is selected during a single channel operation, and transmit the data to the first chip group and the second chip group.