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    Method for forming a high-density circuit structure with interlayer electrical connections method for forming
    92.
    发明授权
    Method for forming a high-density circuit structure with interlayer electrical connections method for forming 失效
    用层压电连接法形成高密度电路结构的方法

    公开(公告)号：US5891606A

    公开(公告)日：1999-04-06

    申请号：US727832

    申请日：1996-10-07

    Applicant: Vernon L. Brown

    Inventor： Vernon L. Brown

    IPC: H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  G03F7/00

    CPC classification number: H05K3/4069 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/0236 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10378 ,  H05K2203/1453 ,  H05K3/0023 ,  H05K3/184 ,  H05K3/465 ,  H05K3/4661

    Abstract: A process for forming a double-sided or multi-layered circuit structure entailing the use of a fill material that forms a conductive connection between the layers of the circuit structure and photodefinable resins that form permanent dielectric layers and plateable surfaces of the circuit structure. The method includes forming a through-hole in a substrate, and then filling the through-hole with the fill material containing a metal that is catalytic to electroless copper. The fill material forms an electrical connection having oppositely-disposed connection surfaces that are coextensive with opposite surfaces of the substrate. A first photodefinable dielectric layer is then formed on each surface of the substrate, including the connection surfaces, and openings are photoimaged and developed in the dielectric layers to expose a portion of each connection surface. A second dielectric layer is then formed over each of the first dielectric layers and the exposed portions of the connection surfaces, with an opening being formed in each of the second dielectric layers to re-expose the portions of the connection surfaces and contiguous surface portions of the first dielectric layers. The exposed surface portions of the first dielectric layers and the exposed portions of the connection surfaces are then electrolessly plated with copper to form conductor traces on each side of the substrate. As a result, the traces electrically contact the connection surfaces, such that traces on opposite sides of the circuit structure are interconnected with the connection formed by the fill material in the through-hole.

    Abstract translation: 一种用于形成双面或多层电路结构的方法，其需要使用形成电路结构层之间的导电连接的填充材料和形成电路结构的永久电介质层和可平板表面的可光限定树脂。 该方法包括在基底中形成通孔，然后用含有对无电铜催化的金属的填充材料填充通孔。 填充材料形成具有相对设置的连接表面的电连接，该连接表面与衬底的相对表面共同延伸。 然后在基板的每个表面上形成第一可光致电介质层，包括连接表面，并且在电介质层中对开口进行光刻和显影以暴露每个连接表面的一部分。 然后在每个第一电介质层和连接表面的暴露部分上形成第二电介质层，其中开口形成在每个第二电介质层中，以重新暴露连接表面和连续表面部分的部分 第一介电层。 然后将第一介电层的暴露表面部分和连接表面的暴露部分用铜无电镀，以在基板的每一侧上形成导体迹线。 结果，迹线电连接到连接表面，使得电路结构的相对侧上的迹线与由通孔中的填充材料形成的连接互连。

    Printed circuits and base materials having low Z-axis thermal expansion
    93.
    发明授权
    Printed circuits and base materials having low Z-axis thermal expansion 失效
    具有低Z轴热膨胀的印刷电路和基材

    公开(公告)号：US5264065A

    公开(公告)日：1993-11-23

    申请号：US698848

    申请日：1991-05-13

    Applicant: Thomas S. Kohm

    Inventor： Thomas S. Kohm

    IPC: H05K1/03 ,  H05K3/46 ,  C23C26/00

    CPC classification number: H05K1/0373 ,  H05K2201/0209 ,  H05K2201/0236 ,  H05K2201/0239 ,  H05K2201/0245

    Abstract: A base material for printed wiring boards is formed by laminating together layers of prepregs of woven cloth impregnated with a thermosetting polymeric resin varnish. The varnish has an inorganic filler which is present in an amount sufficient to provide the base material with an average coefficient of thermal expansion along its Z-axis between 30.degree. C. and 270.degree. C. which is equal to or less than the coefficient of thermal expansion of copper from 30.degree. C. to 270.degree. C. plus the maximum elongation at 270.degree. C. of copper suitable for forming a conductive pattern on hole walls of printed wiring boards. Printed wiring boards manufactured on the base material by additive or subtractive processes are resistant to failure from thermal stress or thermal cycling.

    Process for preparing multilayer printed circuit boards
    96.
    发明授权
    Process for preparing multilayer printed circuit boards 失效
    制备多层印刷电路板的工艺

    公开(公告)号：US4761303A

    公开(公告)日：1988-08-02

    申请号：US929640

    申请日：1986-11-10

    Applicant: Stanley J. Ruszczyk ,  Donald R. Ferrier ,  Gary B. Larson ,  Daniel Gallegos ,  Steven A. Castaldi

    Inventor： Stanley J. Ruszczyk ,  Donald R. Ferrier ,  Gary B. Larson ,  Daniel Gallegos ,  Steven A. Castaldi

    IPC: B05D3/04 ,  B05D3/10 ,  B05D5/12 ,  H05K1/00 ,  H05K3/18 ,  H05K3/46

    CPC classification number: H05K3/181 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0236 ,  H05K2203/1157 ,  H05K2203/125 ,  H05K3/184 ,  H05K3/4602 ,  Y10S428/901

    Abstract: Multilayer printed circuit boards are fabricated by preparing a first layer in conventional manner by forming a resist image on a copper clad substrate, etching away unwanted copper, removing the resist from the circuit pattern and optionally applying a dielectric mask such as conventional solder mask to selected portions of the circuit pattern. A second layer, and optionally one or more subsequent layers, are fabricated by providing an image of a second circuit pattern in a predetermined location on said first layer, the image being formed using a suspension of cuprous oxide in a curable resin material. The image is cured at least partially and subjected to chemical reduction to convert at least a portion of the cuprous oxide to metallic copper such that the unreduced cuprous oxide in resin serves as a dielectric layer. The image is then electrolessly plated with copper to build up the circuit pattern and the latter is selectively coated with a dielectric mask before repeating the cycle to build up one or more additional layers. Solder can be applied to selected areas of any of said printed circuit layers at any appropriate time during fabrication.The above method of fabrication has advantages of economy of time, materials and labor as compared with methods hitherto employed to prepare multilayer boards in which a plurality of single boards are fabricated individually and then assembled as a sandwich or laminate by application of heat and pressure.

    Abstract translation: 通过在铜包覆基板上形成抗蚀剂图像，蚀刻不需要的铜，从电路图案去除抗蚀剂并且可选地将诸如常规焊接掩模的电介质掩模施加到所选择的绝缘掩模上，以常规方式制备第一层来制造多层印刷电路板 部分电路图案。 通过在所述第一层上的预定位置提供第二电路图案的图像来制造第二层和任选的一个或多个后续层，该图像使用可氧化树脂材料中的氧化亚铜的悬浮液形成。 图像至少部分固化并进行化学还原以将至少一部分氧化亚铜转化为金属铜，使得树脂中未还原的氧化亚铜用作电介质层。 然后，图像用铜无电镀以建立电路图案，并且在重复该循环以建立一个或多个附加层之前，将图像选择性地涂覆有电介质掩模。 可以在制造期间的任何适当时间将焊料施加到任何所述印刷电路层的选定区域。 上述制造方法与迄今为止用于制备多个单板的多层板的方法相比，具有经济的时间，材料和劳动的优点，然后通过施加热和压力将其组装成夹层或层压体。

    Modified hectorite for electroless plating
    99.
    发明授权
    Modified hectorite for electroless plating 失效
    改性锂蒙脱石进行化学镀

    公开(公告)号：US3928663A

    公开(公告)日：1975-12-23

    申请号：US45701274

    申请日：1974-04-01

    Applicant: AMP INC

    Inventor： REDMOND JOHN PETER ,  ANDREWS DANIEL MARSHALL ,  BROOKS CHARLES PARSONS ,  CINALLI DOMINIC A ,  MERLINA JOSEPH FRANCIS

    IPC: C23C18/20 ,  H05K1/03 ,  H05K3/18 ,  C23C3/02 ,  B05D3/04

    CPC classification number: C23C18/20 ,  C23C18/2013 ,  C23C18/2066 ,  C23C18/2086 ,  C23C18/22 ,  H05K1/0373 ,  H05K3/181 ,  H05K2201/0209 ,  H05K2201/0236

    Abstract: A method and composition of matter useful for rendering an insulating material, self-catalytic to deposition of electroless metal from solutions thereof are shown. A base exchangeable clay material such as hectorite is base exchanged with a source of cations of a metal selected from Group I-B and VIII of the Periodic Table of Elements, preferably nickel or copper, and thereafter, the cation exchanged hectorite is heated under reducing conditions. This thermal treatment activates the exchanged hectorite as a catalyst to induce metal deposition in electroless plating baths. Without such a treatment the exchanged hectorite is not catalytic. The structure of the hectorite is altered by the thermal treatment as it no longer swells or gels when immersed in water. In addition the mechanical strength of the material is increased by the ''''sintering like'''' treatment. The modified base exchanged material can be incorporated or coated on insulating materials to provide the exterior or interior surfaces thereof with a catalytic sensitivity to deposition of electroless metal. The methods and compositions are useful in processes for manufacture of printed circuitry on substrates such as films, glass reinforced laminates, tapes, and boards. Methods of molding printed circuit substrates in desired geometrical form with vias located in predetermined pattern are disclosed along with chemical and mechanical methods of etching the surface of resin to expose base exchanged mineral that serves as the catalyst for electroless plating.

    Abstract translation: 示出了用于提供绝缘材料的物质的方法和组成，其自催化以从其溶液沉积无电金属。 碱土交换性粘土材料如锂蒙脱石与选自元素周期表第I-B和VIII族的金属的阳离子源进行碱交换，优选镍或铜，然后在还原条件下加热阳离子交换的锂蒙脱石。

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