公开(公告)号：US20120175162A1

公开(公告)日：2012-07-12

申请号：US13428523

申请日：2012-03-23

Applicant: Jee Soo MOK ,  Jun Heyoung PARK

Inventor： Jee Soo MOK ,  Jun Heyoung PARK

IPC: H05K1/11

CPC classification number: H05K3/4069 ,  H05K3/107 ,  H05K3/386 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2203/0278 ,  H05K2203/1461 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T156/109

Abstract: A printed circuit board having an insulating layer; circuit patterns formed on both surfaces of the insulating layer in order to be embedded in the insulating layer; and a bump formed to pass through the insulating layer in order to electrically connect the circuit patterns formed on both surfaces of the insulating layer.

Abstract translation: 一种具有绝缘层的印刷电路板; 形成在绝缘层的两个表面上的电路图案，以便嵌入绝缘层中; 以及形成为穿过绝缘层的凸块，以便电连接形成在绝缘层的两个表面上的电路图案。

公开(公告)号：US08217276B2

公开(公告)日：2012-07-10

申请号：US10410434

申请日：2003-04-10

Applicant: Kentaro Fujii ,  Yoshio Watanabe ,  Toru Takebe

Inventor： Kentaro Fujii ,  Yoshio Watanabe ,  Toru Takebe

IPC: H05K1/03

CPC classification number: H05K3/462 ,  H05K3/064 ,  H05K3/321 ,  H05K3/386 ,  H05K3/423 ,  H05K3/4623 ,  H05K3/4647 ,  H05K3/4658 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer printed circuit board which can surely establish interlayer connection with low resistance. The multilayer printed circuit board comprises: a first substrate having a conductive pattern on one face and a non-penetration connection hole on the other face, for exposing the conductive pattern to outside; a second substrate having a conductive pattern formed on a face opposed to the other face of first substrate and a conductive bump on the conductive pattern integrally. The first substrate and the second substrate are integrated by engaging the bump of the second substrate with the connection hole of the first substrate and by intervening a conductive cement between the bumps and the conductive pattern exposed to outside from the connection holes.

Abstract translation: 一种多层印刷电路板，可以可靠地建立具有低电阻的层间连接。 所述多层印刷电路板包括：在一个面上具有导电图案的第一基板和另一面上的非穿透连接孔，用于将导电图案暴露于外部; 第二基板，其具有形成在与第一基板的另一面相对的表面上的导电图案和导电图案上的导电凸块。 第一基板和第二基板通过将第二基板的凸块与第一基板的连接孔接合并且通过在凸起和从连接孔露出到外部的导电图案之间插入导电粘合剂来集成。

公开(公告)号：US08211494B2

公开(公告)日：2012-07-03

申请号：US10540606

申请日：2004-12-15

Applicant: Toshiaki Takenaka ,  Toshikazu Kondou ,  Yukihiro Hiraishi ,  Kunio Kishimoto

Inventor： Toshiaki Takenaka ,  Toshikazu Kondou ,  Yukihiro Hiraishi ,  Kunio Kishimoto

IPC: B05D5/12 ,  B05D3/12

CPC classification number: H05K3/4069 ,  H05K2201/0355 ,  H05K2201/09036 ,  H05K2201/09781 ,  H05K2203/0191 ,  H05K2203/0228 ,  H05K2203/063 ,  H05K2203/1461

Abstract: A mask film, where squeegee cleaning part has been formed at a predetermined position, and another mask film are attached to both sides of a substrate. A through-hole is formed by using a laser, and conductive paste is filled into the through-hole by using a squeezing method. As discussed above, a paste-residue can be prevented on the through-hole, so that a circuit board having high quality of connection can be obtained.

Abstract translation: 已经在预定位置形成刮板清洁部分的掩模膜，并且另一个掩模膜附着到基板的两侧。 通过使用激光形成通孔，并且通过使用挤压方法将导电膏填充到通孔中。 如上所述，可以在通孔上防止糊料残留，从而可以获得具有高连接质量的电路板。

公开(公告)号：US20120160550A1

公开(公告)日：2012-06-28

申请号：US13252777

申请日：2011-10-04

Applicant: Tae Sung JEONG ,  Doo Hwan LEE ,  Seung Eun LEE

Inventor： Tae Sung JEONG ,  Doo Hwan LEE ,  Seung Eun LEE

IPC: H05K1/09 ,  H05K1/16 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H05K2201/0355 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/063 ,  H05K2203/1152 ,  H05K2203/1189 ,  H05K2203/1469 ,  Y10T29/4913

Abstract: Disclosed is a printed circuit board having an embedded electronic component, which includes a first insulating layer, an electronic component disposed in an opening formed in a thickness direction of the first insulating layer and having a metal bump, a polymer layer formed on one side of the first insulating layer and on which the electronic component is seated so that the metal bump of the electronic component perforates the polymer layer, a second insulating layer formed on the other side of the first insulating layer so as to embed the electronic component, a first circuit layer formed on the second insulating layer, and a second circuit layer formed on the polymer layer so as to be directly electrically connected to the metal bump that perforates the polymer layer, and in which roughness is formed on the polymer layer so that the force of adhesion of the polymer layer to a plating layer is enhanced, thus ensuring reliability of the electrical connection of a circuit layer which is subsequently formed.

Abstract translation: 公开了一种具有嵌入式电子部件的印刷电路板，其包括第一绝缘层，设置在沿第一绝缘层的厚度方向形成的开口中并具有金属凸块的电子部件，形成在第一绝缘层的一侧的聚合物层 第一绝缘层，并且电子部件就座于其上，使得电子部件的金属凸块穿透聚合物层;第二绝缘层，形成在第一绝缘层的另一侧上以嵌入电子部件;第一绝缘层， 形成在第二绝缘层上的电路层和形成在聚合物层上的第二电路层，以直接电连接到穿透聚合物层的金属凸块，并且在聚合物层上形成粗糙度，使得力 增强了聚合物层对镀层的粘附性，从而确保电路层的电连接的可靠性， 随后形成。

公开(公告)号：US20120148862A1

公开(公告)日：2012-06-14

申请号：US13396334

申请日：2012-02-14

Applicant: Terumasa Moriyama ,  Kengo Kaminaga

Inventor： Terumasa Moriyama ,  Kengo Kaminaga

IPC: B32B15/04 ,  H05K3/38

CPC classification number: H05K3/384 ,  C23C28/00 ,  C23C28/321 ,  C23C28/345 ,  C23C28/3455 ,  C25D3/562 ,  C25D3/565 ,  C25D7/0614 ,  H05K2201/0239 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10T428/12438 ,  Y10T428/12472 ,  Y10T428/12569 ,  Y10T428/12583 ,  Y10T428/1259 ,  Y10T428/12618 ,  Y10T428/1266 ,  Y10T428/12792 ,  Y10T428/12847 ,  Y10T428/12903 ,  Y10T428/12944 ,  Y10T428/263 ,  Y10T428/27 ,  Y10T428/273

Abstract: A copper foil for a printed circuit board is provided. The copper foil includes a layer including nickel, zinc, a compound of nickel and that of zinc (hereinafter referred to as a “nickel zinc layer”) on a roughened surface of a copper foil and a chromate film layer on the nickel zinc layer. The zinc add-on weight per unit area of the nickel zinc layer is 180 μg/dm2 or more and 3500 μg/dm2 or less, and the nickel weight ratio in the nickel zinc layer {nickel add-on weight/(nickel add-on weight+zinc add-on weight)} is 0.38 or more and 0.7 or less. This surface treatment technology of a copper foil is able to effectively prevent the circuit corrosion phenomenon in cases of laminating a copper foil on a resin base material and using a sulfuric acid hydrogen peroxide etching solution to perform soft etching to the circuit.

Abstract translation: 提供了用于印刷电路板的铜箔。 铜箔包括在铜箔的粗糙表面上的镍，锌，镍化合物和锌的化合物（以下称为“镍锌层”）的层和镍锌层上的铬酸盐膜层。 镍锌层的单位面积的锌添加量为180μg/ dm 2以上且3500μg/ dm 2以下，镍锌层的镍重量比（镍附加重量/（镍添加量） 重量+锌附加重量）}为0.38以上且0.7以下。 铜箔的表面处理技术能够有效地防止在树脂基材上层叠铜箔并使用硫酸过氧化氢蚀刻溶液对电路进行软蚀刻的情况下的电路腐蚀现象。

公开(公告)号：US20120141777A1

公开(公告)日：2012-06-07

申请号：US13375296

申请日：2010-04-20

Applicant: Yasushi Idemoto ,  Ryuichi Sato ,  Naohiko Abe

Inventor： Yasushi Idemoto ,  Ryuichi Sato ,  Naohiko Abe

IPC: B32B18/00 ,  C25D13/02 ,  B05D3/02 ,  B32B15/04

CPC classification number: H05K1/162 ,  C23C18/1208 ,  C23C18/1254 ,  C25D13/02 ,  H05K1/0306 ,  H05K3/022 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/135 ,  Y10T428/252 ,  Y10T428/265 ,  Y10T428/31678

Abstract: The object of the present invention is to provide a metal layer with an insulating layer which is uniform and thin and can be produced in low cost. To achieve the object, a laminate composed of a ceramic insulating layer and a metal layer characterized in that the ceramic insulating layer has a binder provided among ceramic particles constituting a ceramic particle film formed by electrophoretic deposition of the ceramic particles is employed. The laminate can be suitably used as a base material for production of various types of electronic devices, the circuit formation of printed wiring boards, semiconductor circuits and circuits including semiconductor circuits, and capacitors utilizing dielectric performance of the ceramic insulating layer.

Abstract translation: 本发明的目的是提供一种具有均匀且薄而可以以低成本制造的绝缘层的金属层。 为了实现该目的，采用由陶瓷绝缘层和金属层组成的层压体，其特征在于，陶瓷绝缘层具有在构成通过陶瓷颗粒的电泳沉积形成的陶瓷颗粒膜的陶瓷颗粒中提供的粘合剂。 该层压体可以适合用作生产各种类型的电子器件的基材，印刷电路板的电路形成，半导体电路和包括半导体电路的电路，以及利用陶瓷绝缘层的介电性能的电容器。

公开(公告)号：US08187922B2

公开(公告)日：2012-05-29

申请号：US12557896

申请日：2009-09-11

Applicant: Zaid Aboush ,  Peter John Robinson

Inventor： Zaid Aboush ,  Peter John Robinson

IPC: H01L21/00

CPC classification number: H05K3/0023 ,  H01L23/3128 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0393 ,  H05K2201/0355 ,  H05K2201/0394 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A low cost flexible substrate is described which comprises a thin metal foil and a layer of solder mask. The metal foil layer is patterned to create tracks and lands for solder bonding and/or wirebonding and the layer of solder mask is patterned to create openings for solder bonding, wirebonding and/or for mounting the die. The substrate may be used as a package substrate to create a packaged die or may be used as a replacement for more expensive flexible printed circuit boards.

Abstract translation: 描述了一种低成本的柔性基板，其包括薄金属箔和一层阻焊层。 图案化金属箔层以产生用于焊接和/或引线接合的轨道和焊盘，并且图案化阻焊层以产生用于焊接，引线键合和/或用于安装管芯的开口。 衬底可以用作封装衬底以形成封装的裸片，或者可以用来代替更昂贵的柔性印刷电路板。

公开(公告)号：US08183090B2

公开(公告)日：2012-05-22

申请号：US12856168

申请日：2010-08-13

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H05K3/10

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部上的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US20120114966A1

公开(公告)日：2012-05-10

申请号：US13354176

申请日：2012-01-19

Applicant: Wei-Hsing TUAN ,  Shao-Kuan Lee

Inventor： Wei-Hsing TUAN ,  Shao-Kuan Lee

IPC: B32B15/04 ,  B23K31/02

CPC classification number: B32B15/20 ,  B32B18/00 ,  B32B2311/00 ,  B32B2315/02 ,  B32B2457/00 ,  C04B37/026 ,  C04B2235/6584 ,  C04B2235/9607 ,  C04B2237/062 ,  C04B2237/12 ,  C04B2237/122 ,  C04B2237/123 ,  C04B2237/125 ,  C04B2237/34 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/407 ,  C04B2237/54 ,  C04B2237/56 ,  C04B2237/58 ,  C04B2237/597 ,  C04B2237/60 ,  C04B2237/704 ,  C04B2237/706 ,  C04B2237/708 ,  C04B2237/72 ,  H01L23/3735 ,  H01L2224/48091 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/181 ,  H05K3/388 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2203/072 ,  Y10T428/12479 ,  Y10T428/249984 ,  H01L2924/00014

Abstract: A ceramic/metal composite structure includes an aluminum oxide substrate, an interface bonding layer and a copper sheet. The interface bonding layer is disposed on the aluminum oxide substrate. The copper sheet is disposed on the interface bonding layer. The interface bonding layer bonds the aluminum oxide substrate to the copper sheet. Some pores are formed near or in the interface bonding layer. A porosity of the interface bonding layer is substantially smaller than or equal to 25%. A method of manufacturing the ceramic/metal composite structure is also provided.

Abstract translation: 陶瓷/金属复合结构包括氧化铝衬底，界面粘合层和铜片。 界面接合层设置在氧化铝基板上。 铜片设置在界面结合层上。 界面结合层将氧化铝基板与铜片结合。 在界面结合层附近或之中形成一些孔。 界面结合层的孔隙率基本上小于或等于25％。 还提供了一种制造陶瓷/金属复合结构体的方法。

公开(公告)号：US20120111613A1

公开(公告)日：2012-05-10

申请号：US13384084

申请日：2010-07-07

Applicant: Ryoichi Oguro ,  Kouji Kase ,  Kazuhiro Hoshino

Inventor： Ryoichi Oguro ,  Kouji Kase ,  Kazuhiro Hoshino

IPC: H05K1/09 ,  C23C28/02 ,  B32B15/04 ,  H05K1/02 ,  B32B15/01

CPC classification number: C25D5/48 ,  C23C30/00 ,  C25D1/04 ,  C25D3/562 ,  C25D5/34 ,  C25D7/0628 ,  C25D11/38 ,  H05K1/167 ,  H05K3/384 ,  H05K3/389 ,  H05K2201/0355 ,  H05K2203/0307 ,  Y10T428/12049 ,  Y10T428/12076

Abstract: A copper foil with a resistance layer is provided, wherein the variation value is small when it is made into a resistance element, the adhesion with the resin substrate to be laminated with is able to be sufficiently maintained, which has an excellent characteristics as a resistance element for a rigid and a flexible substrate. A copper foil with a resistance layer of the present invention comprises a copper foil on one surface of which a metal layer or alloy layer is formed from which a resistance element is to be formed, the surface of the metal layer or alloy layer being subjected to a roughening treatment with nickel particles. A method of production of a copper foil with a resistance layer of the present invention comprises: forming a resistance layer of phosphorus-containing nickel on a matte surface of an electrodeposited copper foil having crystals comprised of columnar crystal grains wherein a foundation of the matte surface is within a range of 2.5 to 6.5 μm in terms of Rz value prescribed in JIS-B-0601; and performing roughening treatment to a surface of the resistance layer with nickel particles wherein a roughness is within a range of 4.5 to 8.5 μm in terms of Rz value prescribed in JIS-B-0601. The alloy layer is for example formed from phosphorus-containing nickel.

Abstract translation: 提供了具有电阻层的铜箔，其中当制成电阻元件时其变化值较小，能够充分保持与要层压的树脂基板的粘附性，其具有作为电阻的优异特性 用于刚性和柔性基底的元件。 本发明的具有电阻层的铜箔的一个表面上形成有形成有电阻元件的金属层或合金层的铜箔，金属层或合金层的表面经受 用镍颗粒进行粗糙处理。 本发明的具有电阻层的铜箔的制造方法包括：在具有由柱状晶粒构成的结晶的电沉积铜箔的无光泽表面上形成含磷镍电阻层，其中， 在JIS-B-0601中规定的Rz值为2.5〜6.5μm的范围内。 并且以JIS-B-0601中规定的Rz值为基准的粗糙度在4.5〜8.5μm的范围内的镍粒子对电阻层的表面进行粗糙化处理。 合金层例如由含磷的镍形成。