公开(公告)号：US08247898B2

公开(公告)日：2012-08-21

申请号：US12702804

申请日：2010-02-09

Applicant: Masahiro Ono

Inventor： Masahiro Ono

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/0218 ,  H05K1/095 ,  H05K3/284 ,  H05K2201/0919 ,  H05K2203/1316 ,  H01L2224/81

Abstract: A module substrate has an interconnection electrode that is exposed at a side end face thereof. A semiconductor component including an IC chip is mounted on the module substrate. A molded part comprising a resin is formed so as to cover at least a part of the semiconductor component. A coating with higher heat conductivity than the molded part is formed on the surface of the molded part by applying a paste made of material with higher heat conductivity than the molded part. This improves heat dissipation. The coating can be formed such that it extends to the surface of the main substrate on which the module substrate with the semiconductor component is mounted and comes into contact with the interconnection electrode on the surface of the main substrate. This further improves heat dissipation.

Abstract translation: 模块基板具有在其侧端面露出的互连电极。 包括IC芯片的半导体部件安装在模块基板上。 形成包含树脂的成型部，以覆盖半导体部件的至少一部分。 通过施加由比模制部件更高的导热性的材料制成的糊料，在模制部件的表面上形成具有比模制部件更高导热性的涂层。 这改善了散热。 涂层可以形成为使得其延伸到其上安装有半导体部件的模块基板的主基板的表面，并且与主基板的表面上的互连电极接触。 这进一步改善了散热。

公开(公告)号：US08150071B2

公开(公告)日：2012-04-03

申请号：US12376602

申请日：2007-09-19

Applicant: Mitsuru Kobayashi

Inventor： Mitsuru Kobayashi

IPC: H03G3/00

CPC classification number: H05K1/142 ,  H01R13/514 ,  H04B1/08 ,  H04R25/60 ,  H04R25/604 ,  H05K1/0284 ,  H05K1/0298 ,  H05K1/119 ,  H05K1/183 ,  H05K3/326 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10037 ,  H05K2201/10083 ,  H05K2201/1059 ,  H05K2201/209

Abstract: An appliance is provided which can be easily assembled, assures quality and reliability, and can be downsized. A voice output unit includes: a power source supplying power; a signal processing module which processes voice signals received from an external source, and amplifies the processed voice signals processed; a speaker module transmitting the amplified voice signals as voice signals; and a stereoscopic circuit board on which the power source, signal processing module, and speaker module are assembled, and includes electrodes which are in electric contact with electrodes of the foregoing components.

Abstract translation: 提供易于组装的设备，确保质量和可靠性，并且可以小型化。 语音输出单元包括：电源供电; 信号处理模块，处理从外部源接收的语音信号，并放大所处理的已处理语音信号; 将放大的语音信号作为语音信号发送的扬声器模块; 以及其上组装有电源，信号处理模块和扬声器模块的立体电路板，并且包括与上述部件的电极电接触的电极。

公开(公告)号：US08141245B2

公开(公告)日：2012-03-27

申请号：US12344643

申请日：2008-12-29

Applicant: Kevin C. Olson ,  Alan E. Wang ,  Peter Elenius ,  Thomas W. Goodman

Inventor： Kevin C. Olson ,  Alan E. Wang ,  Peter Elenius ,  Thomas W. Goodman

IPC: H01K3/10

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Abstract translation: 多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片的另一表面的绝缘底层和覆盖 导电片的边缘。 绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。 无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。

公开(公告)号：US08110751B2

公开(公告)日：2012-02-07

申请号：US12411847

申请日：2009-03-26

Applicant: Dong You Kim ,  Yong Tae Kyeon ,  Ja Yong Ku

Inventor： Dong You Kim ,  Yong Tae Kyeon ,  Ja Yong Ku

IPC: H05K1/11

CPC classification number: H05K1/117 ,  H05K1/0298 ,  H05K3/403 ,  H05K2201/09172 ,  H05K2201/0919

Abstract: The present invention relates to a semiconductor memory module and an electronic component socket for coupling with the same. A printed circuit board of the semiconductor memory module includes three signal pad arrays longitudinally formed in a row on one sides of a first surface, a second surface and a third surface thereof. Each signal pad array includes a plurality of signal pads. An electronic component socket for coupling with the printed circuit board includes thee pin arrays. Thus, an increased number of the signal pads can be provided while retaining the size of the memory module and the electronic component socket.

Abstract translation: 本发明涉及半导体存储器模块和与其耦合的电子元件插座。 半导体存储器模块的印刷电路板包括在第一表面，第二表面和第三表面的一侧纵向形成为一排的三个信号垫阵列。 每个信号焊盘阵列包括多个信号焊盘。 用于与印刷电路板耦合的电子元件插座包括引脚阵列。 因此，可以在保持存储器模块和电子部件插座的尺寸的同时提供增加数量的信号焊盘。

公开(公告)号：US08089776B2

公开(公告)日：2012-01-03

申请号：US11425003

申请日：2006-06-19

Applicant: Tobias Kjerrman ,  Georgeta Anton ,  Pontus Bartilsson ,  Paul Larsson ,  Mikael Hansson ,  Bengt Mattsson

Inventor： Tobias Kjerrman ,  Georgeta Anton ,  Pontus Bartilsson ,  Paul Larsson ,  Mikael Hansson ,  Bengt Mattsson

IPC: H05K7/00

CPC classification number: H01H1/5805 ,  H01H1/403 ,  H01H2231/022 ,  H04M1/236 ,  H05K1/0298 ,  H05K3/403 ,  H05K2201/0919 ,  H05K2201/10053 ,  H05K2201/10446

Abstract: A switch configured to contact an exposed contact on an edge of a multilayer circuit board when selectively activated. The switch is particularly useful for electronic equipment such as mobile phones, PDA's, etc. where space for key contacts on the circuit board is limited. By facilitating connection to terminals formed on edges of a circuit board and/or edges of layers of multilayer circuit boards, the switch provides additional options for button locations on the electronic device heretofore requiring routing of wiring.

Abstract translation: 一种开关，其被配置为当选择性地激活时接触多层电路板的边缘上的暴露接触。 该开关对于诸如手机，PDA等的电子设备特别有用，其中电路板上的键触点的空间受到限制。 通过促进连接到形成在电路板的边缘上的端子和/或多层电路板的边缘的边缘，开关为电路设备上的按钮位置提供额外的选项，此前需要布线。

公开(公告)号：US08077478B2

公开(公告)日：2011-12-13

申请号：US11908726

申请日：2006-03-15

Applicant: Masahiro Takatori ,  Yukihiro Ishimaru

Inventor： Masahiro Takatori ,  Yukihiro Ishimaru

IPC: H05K1/11 ,  H05K1/14 ,  H05K7/00

CPC classification number: H01L25/0652 ,  H01L23/5385 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0268 ,  H05K1/112 ,  H05K1/117 ,  H05K1/185 ,  H05K3/4611 ,  H05K2201/0919 ,  H05K2201/09845 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A module board has a configuration in which a first circuit board, a first composite sheet, a second circuit board, a second composite sheet, and a third circuit board are laminated in this order. Inspection terminals are arranged in a matrix shape in a predetermined region on an upper surface of the third circuit board. Electronic components are mounted on the first and second circuit boards. The inspection terminals are electrically connected to the electronic components mounted on the first and second circuit boards through vias and wiring patterns.

Abstract translation: 模块板具有以下顺序构造第一电路板，第一复合片，第二电路板，第二复合片和第三电路板。 检查端子在第三电路板的上表面上的预定区域中以矩阵形状布置。 电子部件安装在第一和第二电路板上。 检查端子通过通孔和布线图形电连接到安装在第一和第二电路板上的电子部件。

公开(公告)号：US08023282B2

公开(公告)日：2011-09-20

申请号：US11856858

申请日：2007-09-18

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H01R12/16

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/19107 ,  H05K1/142 ,  H05K3/4611 ,  H05K2201/058 ,  H05K2201/091 ,  H05K2201/09109 ,  H05K2201/0919 ,  H05K2201/09481 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T428/24322 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

Abstract translation: 多层基板的混合结构包括第一多层基板和第二多层基板。 第一多层基板交替地堆叠第一金属层，第一介电层并具有VIA。 第一金属层的边界区域与相应的第一介电层的边界区域连接。 边界区域与相邻的第一金属层和相邻的第一介电层分离。 第二多层基板交替堆叠第二金属层和第二电介质层。 第二金属层的边界区域与相应的第二电介质层的边界区域连接。 边界区域与相邻的第二金属层和相邻的第二介电层分离。 VIA位于第一电介质层的边界区，并且每个VIA具有导电体，以将一个第一金属层与一个第二金属层连接。

公开(公告)号：US20110220403A1

公开(公告)日：2011-09-15

申请号：US12762093

申请日：2010-04-16

Applicant: Hsien-Chieh Lin

Inventor： Hsien-Chieh Lin

IPC: H05K1/11

CPC classification number: H05K3/403 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K3/3405 ,  H05K3/4602 ,  H05K2201/0919 ,  H05K2201/10446 ,  H01L2924/00

Abstract: The invention provides a side packaged type printed circuit board. The side packaged type printed circuit board includes a circuit substrate having a surface and an adjacent side surface. An inner circuit covers a portion of the surface. A first side electrical connecting pad electrically connects to the inner circuit, wherein the first side electrical connecting pad and the inner circuit are in the same additional layer.

Abstract translation: 本发明提供一种侧面封装型印刷电路板。 侧面封装型印刷电路板包括具有表面和相邻侧表面的电路基板。 内部电路覆盖表面的一部分。 第一侧电连接垫电连接到内部电路，其中第一侧电连接焊盘和内部电路处于相同的附加层中。

公开(公告)号：US08014164B2

公开(公告)日：2011-09-06

申请号：US13015739

申请日：2011-01-28

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H05K7/00

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/19107 ,  H05K1/142 ,  H05K3/4611 ,  H05K2201/058 ,  H05K2201/091 ,  H05K2201/09109 ,  H05K2201/0919 ,  H05K2201/09481 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T428/24322 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

公开(公告)号：US20110124154A1

公开(公告)日：2011-05-26

申请号：US13015725

申请日：2011-01-28

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H01L21/50

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/19107 ,  H05K1/142 ,  H05K3/4611 ,  H05K2201/058 ,  H05K2201/091 ,  H05K2201/09109 ,  H05K2201/0919 ,  H05K2201/09481 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T428/24322 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.