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    WIRING SUBSTRATE
    91.
    发明申请
    WIRING SUBSTRATE 有权
    接线基板

    公开(公告)号：US20110308840A1

    公开(公告)日：2011-12-22

    申请号：US13075838

    申请日：2011-03-30

    Applicant: Takahiro OOI ,  Yoshihiro MORITA ,  Akiko MATSUI ,  Tetsuro YAMADA ,  Mitsuhiko SUGANE ,  Takahide MUKOYAMA

    Inventor： Takahiro OOI ,  Yoshihiro MORITA ,  Akiko MATSUI ,  Tetsuro YAMADA ,  Mitsuhiko SUGANE ,  Takahide MUKOYAMA

    IPC: H05K1/02 ,  H01R43/00

    CPC classification number: H05K1/0248 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0269 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09272 ,  H05K2203/166 ,  H05K2203/167

    Abstract: A wiring substrate includes differential wirings; a first insulating layer adjacent to one side of the differential wirings, including first fiber bundles parallel to the differential wirings; a second insulating layer adjacent to another side of the differential wirings, including second fiber bundles parallel to the differential wirings and disposed by the same pitch as the first fiber bundles; a third insulating layer on the first insulating layer on a side opposite to the differential wirings, including third fiber bundles in parallel to the differential wirings; and a fourth insulating layer on the second insulating layer on a side opposite to the differential wirings, including fourth fiber bundles in parallel to the differential wirings. Intervals of the third and fourth fiber bundles are respectively narrower than intervals of the first and second fiber bundles. The differential wirings are disposed between adjacent first fiber bundles, and between adjacent second fiber bundles.

    Abstract translation: 布线基板包括差分布线; 与所述差分布线的一侧相邻的第一绝缘层，包括平行于所述差分布线的第一光纤束; 与所述差分布线的另一侧相邻的第二绝缘层，包括与所述差分布线平行并且以与所述第一纤维束相同的间距设置的第二纤维束; 在所述第一绝缘层上的与所述差分布线相反的一侧的第三绝缘层，包括与所述差分布线平行的第三纤维束; 以及在所述第二绝缘层上的与所述差分布线相反的一侧的第四绝缘层，包括与所述差分布线平行的第四纤维束。 第三和第四纤维束的间隔分别比第一和第二纤维束的间隔窄。 差分布线设置在相邻的第一纤维束之间以及相邻的第二纤维束之间。

    EDGE CONNECTOR AND MANUFACTURING METHOD THEREFOR
    94.
    发明申请
    EDGE CONNECTOR AND MANUFACTURING METHOD THEREFOR 失效
    边缘连接器及其制造方法

    公开(公告)号：US20100151703A1

    公开(公告)日：2010-06-17

    申请号：US12465675

    申请日：2009-05-14

    Applicant: Shinji Shibao

    Inventor： Shinji Shibao

    IPC: H01R12/30 ,  C25D5/48 ,  H05K3/10

    CPC classification number: H05K3/242 ,  H01R12/721 ,  H05K1/025 ,  H05K1/117 ,  H05K1/141 ,  H05K1/165 ,  H05K3/0052 ,  H05K2201/0919 ,  H05K2201/09272 ,  H05K2201/09481 ,  H05K2201/09727 ,  H05K2201/10189 ,  H05K2203/175 ,  Y10T29/49155

    Abstract: An edge connector includes, a multilayer printed board having an inner layer and a connector edge, an electronic circuit disposed on the multilayer printed board, an electrical terminal on the multilayer printed board and spaced by a predetermined clearance from the connector edge, an electrical conductor on the multilayer printed board and connected between the electronic circuit and the electrical terminal, a via connected to the electrical terminal and extending to the inner layer of the multilayer printed board, and a lead conductor on the inner layer of the multilayer printed board and connected at one end to the via, another end of the lead conductor being exposed at the connector edge. The electrical terminal is plated. The sum of the length of the via and the length of the lead conductor is less than one-sixth of the wavelength of an electrical signal transmitted.

    Abstract translation: 边缘连接器包括：具有内层和连接器边缘的多层印刷电路板，设置在多层印刷电路板上的电子电路，多层印刷电路板上的电气端子并与连接器边缘隔开预定间隙;电导体 在多层印刷电路板上并连接在电子电路和电气端子之间，连接到电气端子并延伸到多层印刷电路板的内层的通孔以及在多层印刷电路板的内层上的引线导体 在一端到通孔，引线导体的另一端在连接器边缘处露出。 电气端子电镀。 通孔的长度和引线导体的长度之和小于发送的电信号的波长的六分之一。

    FILM PATTERN FORMING METHOD, DEVICE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC APPLIANCE
    96.
    发明申请
    FILM PATTERN FORMING METHOD, DEVICE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC APPLIANCE 有权
    电影图案形成方法，装置，电光设备和电子器具

    公开(公告)号：US20070117233A1

    公开(公告)日：2007-05-24

    申请号：US11556384

    申请日：2006-11-03

    Applicant: Toshimitsu HIRAI ,  Katsuyuki MORIYA

    Inventor： Toshimitsu HIRAI ,  Katsuyuki MORIYA

    IPC: H01L21/00

    CPC classification number: H05K3/1258 ,  G02F2001/136295 ,  H05K3/125 ,  H05K2201/09272 ,  H05K2201/09727 ,  H05K2203/013 ,  H05K2203/0568

    Abstract: A method for forming a film pattern by disposing a functional fluid on a substrate, includes: forming a partition wall that includes a first opening that corresponds to a first film pattern and a second opening that corresponds to a second film pattern; and disposing a droplet of the functional fluid into the first opening, so that the functional fluid is disposed into the second opening by a self-flow of the functional fluid; wherein: the first film pattern is linear; the second film pattern is narrower than the first film pattern, and is connected to the first film pattern at a rear edge thereof; and a front edge of the second film pattern has a missing part in which a corner of a rectangular contour is missing.

    Abstract translation: 通过在基板上设置功能流体来形成膜图案的方法包括：形成分隔壁，其包括对应于第一膜图案的第一开口和对应于第二膜图案的第二开口; 并且将所述功能流体液滴设置在所述第一开口中，使得所述功能流体通过所述功能流体的自身流动而被设置在所述第二开口中; 其中：所述第一膜图案是线性的; 所述第二胶片图案比所述第一胶片图案窄，并且在其后缘与所述第一胶片图案连接; 并且第二胶片图案的前边缘具有缺少矩形轮廓的角部的缺失部分。

    Differential transmission line
    97.
    发明申请
    Differential transmission line 有权
    差动传输线

    公开(公告)号：US20070063782A1

    公开(公告)日：2007-03-22

    申请号：US11601707

    申请日：2006-11-20

    Applicant: Hiroshi Kanno ,  Kazuyuki Sakiyama ,  Ushio Sangawa ,  Tomoyasu Fujishima

    Inventor： Hiroshi Kanno ,  Kazuyuki Sakiyama ,  Ushio Sangawa ,  Tomoyasu Fujishima

    IPC: H01P3/08

    CPC classification number: H01P3/081 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09272

    Abstract: A differential transmission line according to the present invention includes: a substrate 101; a ground conductor layer 105 formed on a rear side of the substrate 101; and a first signal conductor 102a and a second signal conductor 102b disposed in parallel to each other on a front side of the substrate 101. The first signal conductor 102a and the ground conductor layer 105 compose a first transmission line, whereas the second signal conductor 102b and the ground conductor layer 105 compose a second transmission line. The first transmission line and the second transmission line compose a differential transmission line 102c. The differential transmission line 102c includes a curved region 104a, with a straight region 104b being connected to each end of the curved region 104a. In the ground conductor layer 105 in the curved region 104a, a plurality of slots 106a which are orthogonal to a local transmission direction of signals in the curved region 104a are formed, the slots 106a being connected to one another on the inner side of the curvature.

    Abstract translation: 根据本发明的差分传输线包括：基板101; 形成在基板101的后侧的接地导体层105; 以及在基板101的前侧上彼此平行设置的第一信号导体102a和第二信号导体102b。第一信号导体102a和接地导体层105构成第一传输线，而第二信号导体 信号导体102b和接地导体层105构成第二传输线。 第一传输线和第二传输线构成差分传输线102c。 差动传输线102c包括弯曲区域104a，其中直线区域104b连接到弯曲区域104a的每个端部。 在弯曲区域104a中的接地导体层105中，形成与弯曲区域104a中的信号的局部传输方向正交的多个槽106a，槽106a在内部彼此连接 侧面的曲率。

    INTEGRATED CIRCUIT CHIP MODULE
    98.
    发明申请
    INTEGRATED CIRCUIT CHIP MODULE 有权
    集成电路芯片模块

    公开(公告)号：US20070018307A1

    公开(公告)日：2007-01-25

    申请号：US11535115

    申请日：2006-09-26

    Applicant: Kohji SHINOMIYA

    Inventor： Kohji SHINOMIYA

    IPC: H01L23/52 ,  H05K7/00 ,  H05K1/00 ,  H05K1/18

    CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

    Abstract: An integrated circuit chip module includes a first integrated circuit chip including a first power source pad for a first power voltage and an adjacent second power source pad for a second power voltage, the first power voltage being higher than the second power voltage, a second integrated circuit chip including a third power source pad for the first power voltage and an adjacent fourth power source pad for the second power voltage, and a wiring board including a first power source wire electrically connected to the first power source pad, a second power source wire electrically connected to the second power source pad, a third power source wire electrically connected to the third power source pad, and a fourth power source wire electrically connected to the fourth power source pad. Distance between the first and second power source wires is shorter than distance between the first or second power source wires and the third or fourth power source wires, and distance between the third and fourth power source wires is shorter than distance between the first or second power source wires and the third or fourth power source wires.

    Abstract translation: 集成电路芯片模块包括第一集成电路芯片，其包括用于第一电源电压的第一电源焊盘和用于第二电源电压的相邻的第二电源焊盘，所述第一电源电压高于所述第二电源电压，第二集成电路 电路芯片，包括用于第一电源电压的第三电源焊盘和用于第二电源电压的相邻第四电源焊盘;以及布线板，包括电连接到第一电源焊盘的第一电源线，第二电源线 电连接到第二电源焊盘，电连接到第三电源焊盘的第三电源线和电连接到第四电源焊盘的第四电源线。 第一和第二电源线之间的距离短于第一或第二电源线与第三或第四电源线之间的距离，并且第三和第四电源线之间的距离短于第一或第二电源线之间的距离 源极线和第三或第四电源线。

    Method of electroforming a slip ring
    99.
    发明授权
    Method of electroforming a slip ring 有权
    电铸滑环的方法

    公开(公告)号：US06502298B1

    公开(公告)日：2003-01-07

    申请号：US09484417

    申请日：2000-01-18

    Applicant: Barry Kent Witherspoon ,  Larry Dean Vaught

    Inventor： Barry Kent Witherspoon ,  Larry Dean Vaught

    IPC: H01R4306

    CPC classification number: H05K3/4007 ,  H01R39/10 ,  H01R43/10 ,  H05K1/11 ,  H05K3/108 ,  H05K2201/09272 ,  H05K2201/09745 ,  H05K2203/0369 ,  Y10T29/49011 ,  Y10T29/49155 ,  Y10T29/49156

    Abstract: Disclosed is a method of manufacturing a slip ring printed circuit board which includes forming a plurality of concentric spaced electrical contacts on one side of a non-conductive base and forming interconnecting electrical paths on an opposite side of the non-conductive base. The method of manufacturing a slip ring printed circuit board also includes electrically connecting the electrical contacts and the interconnecting electrical paths, depositing copper on the electrical contacts to form electrical rings and etching a groove into each of the electrical rings.

    Abstract translation: 公开了一种制造滑环印刷电路板的方法，其包括在非导电基底的一侧上形成多个同心隔开的电触点，并在非导电基底的相对侧上形成互连电路径。 制造滑环印刷电路板的方法还包括电连接电触头和互连电路径，在电触头上沉积铜以形成电环并将凹槽蚀刻到每个电环中。

    Process to decrease the strength of an electric field produced by a high voltage conductive path of a printed circuit board and printed circuit assembly using same
    100.
    发明授权
    Process to decrease the strength of an electric field produced by a high voltage conductive path of a printed circuit board and printed circuit assembly using same 失效
    降低由印刷电路板上的高压导电路径产生的电场的强度和使用它的印刷电路组件的工艺

    公开(公告)号：US5814203A

    公开(公告)日：1998-09-29

    申请号：US563622

    申请日：1995-11-28

    Applicant: Pascal Gaston Raymond Delporte ,  Pierre Paul Roger Willy Depireux

    Inventor： Pascal Gaston Raymond Delporte ,  Pierre Paul Roger Willy Depireux

    IPC: H05K1/02 ,  H05K3/06 ,  H05K3/24 ,  H05K3/34 ,  C25D5/50

    CPC classification number: H05K3/3473 ,  H05K1/0257 ,  H05K1/0254 ,  H05K2201/09272 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/043 ,  H05K2203/0776 ,  H05K3/062 ,  H05K3/244 ,  H05K3/3494

    Abstract: A process to decrease the strength of an electric field produced by a high voltage conductive path on a printed circuit board and printed circuit assembly using same includes the steps of coating the upper side (5) of the conductive path or track (1) with a thick layer of electrically conductive coating material (4); and reflowing so that the upper edges (8, 9) of the track (1) are also covered with a relatively thick layer of coating material. The track (1) is thus embedded in a mass of coating material having more or less a rounded-shaped cross-section and the sharp upper edges (8, 9) of this track, where a strong electrical field is generally produced, are smoothed. As a result, the strength of the electrical field around the track (1) is reduced. In a preferred embodiment, a second track (13) similar to the first track (1) is created symmetrically thereto on the opposite surface (14) of the printed circuit board (3). This second track (13) is brought to the same potential as the first track (1) and is coated in a same way. Therefore, the electrical fields still produced at the lower edges (10, 11) of the track (1), which are not totally embedded in the mass of coating material because the latter do not adhere on the surface (2) of the printed circuit board (3), are counterbalanced by the electrical fields produced at corresponding opposite edges (15, 16) of the second track (13). The strength of the global electrical field around the tracks (1, 13) is thereby drastically reduced.

    Abstract translation: 降低由印刷电路板上的高压导电路径产生的电场的强度和使用它的印刷电路组件的工艺包括以下步骤：用导电路径或轨道（1）涂覆上侧（5） 厚层的导电涂层材料（4）; 并回流，使得轨道（1）的上边缘（8,9）也被相对厚的涂层材料覆盖。 轨道（1）因此被嵌入到具有或多或少具有圆形横截面的涂层材料块中，并且通常产生强电场的该轨道的锋利的上边缘（8,9）被平滑化 。 结果，轨道（1）周围的电场强度降低。 在优选实施例中，与印刷电路板（3）的相对表面（14）对称地形成类似于第一轨道（1）的第二轨道（13）。 该第二轨道（13）被带到与第一轨道（1）相同的电位并以相同的方式被涂覆。 因此，在轨道（1）的下边缘（10,11）处仍然产生的电场，由于后者不粘附在印刷电路的表面（2）上，所以不完全嵌入涂层材料中 板（3）由在第二轨道（13）的对应的相对边缘（15,16）处产生的电场平衡。 轨道（1,13）周围的全局电场的强度因此大大降低。

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