Abstract:
A highly reliable electrostatic-capacitive-type display device with a touch panel which allows a user to perform finger touch inputting and exhibits excellent detection sensitivity is provided. A transparent conductive film is formed above a back surface of an electrostatic-capacitive-type touch panel so as to block noises generated by a display device. A conductive member is provided to supply a voltage to a transparent conductive film formed above a back surface of the touch panel. An electrode which is formed on the electrostatic-capacitive-type touch panel is divided in accordance with a ratio between the number of X electrodes and the number of Y electrodes. A floating electrode is formed in a gap defined between the electrodes so as to adjust an area of the electrode. Due to the shrinkage of the area of the electrode, it is possible to lower a noise level to a level equal to or lower than a signal level. Accordingly, an S/N ratio is increased thus enhancing detection sensitivity. Further, lines are branched on a flexible printed circuit board and intersecting lines are formed on a back surface of the flexible printed circuit board, and the intersecting lines are made to orthogonally intersect with lines formed on a front surface of the flexible printed circuit board thus lowering line capacitance.
Abstract:
A via structure is disclosed to pass electronic signals from a first conductive pathway formed on a first outermost substrate of a multi-layer PCB to a second conductive pathway formed on a second outermost substrate of the multi-layer PCB. The via structure allows the electronic signals to pass from the first outermost substrate through one or more inner substrates to the second outermost substrate. The one or more inner substrates include one or more closed geometric structures to enclose the via structure.
Abstract:
There is provided a light emitting diode (LED) package substrate including: a substrate including a chip mounting region on which a plurality of LED chips is mountable; a conductive layer including a plurality of electrode patterns disposed on the chip mounting region; and a groove part, forming a dam, wherein the groove part surrounds the chip mounting region and is spaced apart from the chip mounting region by a predetermined interval.
Abstract:
On a circuit substrate on which an adhesive is used to couple electronic or structural components to the substrate, an adhesive dam is positioned to prevent the adhesive from interfering with the operation of the circuit. A contact pad can be provided at a selected location and with a selected shape, and solder deposited on the pad, then reflowed to form the dam. The dam can be a structure soldered to a contact pad, or the dam can be supported at its ends by another structure of the device, so that, at the location where it functions to contain the adhesive, it is not attached to the substrate.
Abstract:
A wiring board with a built-in electronic component includes a core substrate having a penetrating hole formed in the core substrate, an electronic component accommodated in the penetrating hole in the core substrate, a conductive pattern layer formed on a first surface of the core substrate and including a first conductive pattern and a second conductive pattern, and an interlayer insulation layer formed over the conductive pattern layer and the first surface of the core substrate. The second conductive pattern is formed adjacent to a periphery of the penetrating hole and contoured such that a sheet for positioning the electronic component in the penetrating hole is laminated horizontally with respect to the first surface of the core substrate over the penetrating hole.
Abstract:
A packaging structure having an embedded semiconductor element includes: a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; a first metallic frame disposed around the periphery of the opening on the first surface; a semiconductor chip received in the opening and having an active surface formed with a plurality of electrode pads and an opposite inactive surface; two first dielectric layers formed on the active surface and the inactive surface of the chip, respectively; a first wiring layer formed on the first dielectric layer of the first surface; and a first built-up structure disposed on the first dielectric layer and the first wiring layer. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.
Abstract:
A packaging substrate device includes: a first laminate including a first ceramic substrate and a first copper pattern disposed on an upper surface of the first ceramic substrate; and a second laminate disposed over the first copper pattern and including a second ceramic substrate, a second copper pattern that is disposed on an upper surface of the second ceramic substrate, and a through hole extending through the second ceramic substrate and the second copper pattern to expose a copper portion of the first copper pattern. A light emitting semiconductor die can be mounted on the copper portion within the through hole. Efficient heat dissipation can be achieved through the first laminate.
Abstract:
According to one embodiment, a module connection structure designed to connect a module to other modules. The module includes a dielectric layer, a micro-strip path, a projection, and a plurality of gain adjusting lands. The dielectric layer is formed on a substrate. The micro-strip path is provided on the dielectric layer and configured to transmit a transmission signal input to one end portion, to the other end portion. The projection is formed at edges of the substrate, which are adjacent to the other modules, and protruding from the micro-strip path and the dielectric layer toward the other modules. The plurality of gain adjusting lands is formed adjacent to the micro-strip path, for use in adjusting an input/output gain of the module. The gain adjusting lands uncouple from the micro-strip path or other gain adjusting lands couple to the micro-strip path, thereby to adjust the input/output gain of the module.
Abstract:
A combination of an interconnect board and a module board for connecting a plurality of electronic modules to a processing unit is described. The interconnect board comprises a plurality of interconnect data lines connected between a plurality of interconnect board input terminals and interconnect board output terminals. The module board comprises at least one electronic module connected to a module connection input terminal, a plurality of module board data lines connected between a plurality of module board input terminals and a plurality of module board output terminals, and an unconnected module board output terminal. A first one of the interconnect board output terminals is connectable to the module connection input terminal, and the unconnected module board output terminal is connectable to one of the interconnect board input terminals.
Abstract:
A semiconductor device (20) has a plurality of device-side lands (23) which are disposed asymmetrically in relation to an intersection point (B). The plurality of device-side lands (23) include 45 device-side connection lands and four device-side isolation lands. Each of the device-side connection lands is mechanically connected to a printed board (10) via a connection component (30). Each of the device-side isolation lands is mechanically isolated from the printed board (10).