公开(公告)号：US20060180919A1

公开(公告)日：2006-08-17

申请号：US11279972

申请日：2006-04-17

Applicant: Satyendra Chauhan ,  Masood Murtuza

Inventor： Satyendra Chauhan ,  Masood Murtuza

IPC: H01L23/04

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/3452 ,  H05K2201/09709 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2224/0401

Abstract: A package, comprising a substrate having a surface comprising metal traces, a solder mask covering at least a portion of the surface of the substrate, and a first aperture through the solder mask exposing a plurality of metal traces.

Abstract translation: 一种封装，包括具有包括金属迹线的表面的衬底，覆盖衬底的表面的至少一部分的焊接掩模和暴露多个金属迹线的通过焊料掩模的第一孔。

公开(公告)号：US07088590B2

公开(公告)日：2006-08-08

申请号：US10721584

申请日：2003-11-25

Applicant: Brad D. Rumsey

Inventor： Brad D. Rumsey

IPC: H05K7/02

CPC classification number: H05K3/3452 ,  H05K2201/0989 ,  H05K2203/1178 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165

Abstract: A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.

公开(公告)号：US20060125075A1

公开(公告)日：2006-06-15

申请号：US11059143

申请日：2005-02-15

Applicant: Yu-Lin Liao ,  Chien-Te Chen

Inventor： Yu-Lin Liao ,  Chien-Te Chen

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/242 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K3/0052 ,  H05K3/28 ,  H05K3/284 ,  H05K2201/09781 ,  H05K2201/0989 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A flash preventing substrate and a method for fabricating the same are proposed. A core defined with a plurality of substrate units is prepared. A circuit patterning process is performed to form circuit structures on the core corresponding to the substrate units, plating buses between the adjacent substrate units and electrically connected to the circuit structures, and a molding ring surrounding all the substrate units. The molding ring is located at a position predetermined for contacting the substrate with a mold. A solder mask layer covers the circuit structures, the plating buses and the molding ring, and is formed with a plurality of openings therein, such that predetermined portions of the circuit structures are exposed via the openings and serve as electrical input/output connections. During a molding process, the mold can tightly abut against the solder mask layer covering the molding ring to prevent outward flashes of an encapsulating material.

公开(公告)号：US20050277226A1

公开(公告)日：2005-12-15

申请号：US10856269

申请日：2004-05-28

Applicant: Yinon Degani ,  Jericho Jacala

Inventor： Yinon Degani ,  Jericho Jacala

IPC: H01L21/44 ,  H01L23/485 ,  H01L23/498 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/3463 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00014

Abstract: A printed circuit board has, on one surface thereof, a plurality of metallic pads forming or leading to wire traces. The printed circuit board surface is solder mask free and a substantially runless soldering alloy is used to connect I/O solder bumps on a flip chip to the metallic pads.

Abstract translation: 印刷电路板在其一个表面上具有形成或导向导线迹线的多个金属垫。 印刷电路板表面是无焊料掩模，并且使用基本上无润滑的焊接合金将倒装芯片上的I / O焊料凸点连接到金属焊盘。

公开(公告)号：US20050258544A1

公开(公告)日：2005-11-24

申请号：US10848649

申请日：2004-05-18

Applicant: Sung-Jin Kim

Inventor： Sung-Jin Kim

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/111 ,  H05K3/3457 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611

Abstract: A substrate for solder joint is provided, including: a core layer; at least one conductive trace formed on the core layer and having a circular terminal as a pad through which a plurality of hollow portions are formed and expose predetermined portions of the core layer underneath the pad, wherein the hollow portions are arranged at equal intervals and spaced from a periphery of the circular pad; and a solder mask for covering the conductive trace and having at least one opening bordered across each of the hollow portions of the pad, such that part of the pad and part of each of the predetermined portions of the core layer are exposed via the opening, to allow a conductive element to be bonded to the exposed part of the pad and the exposed part of the predetermined portions of the core layer in the opening of the solder mask.

Abstract translation: 提供了一种用于焊接接头的基板，包括：芯层; 形成在所述芯层上的至少一个导电迹线，并且具有圆形端子作为衬垫，通过所述衬垫形成多个中空部分并且暴露所述衬垫下方的所述芯层的预定部分，其中所述中空部分以相等间隔布置并间隔开 从圆形垫的周边; 以及用于覆盖导电迹线并且具有横跨垫的每个中空部分的至少一个开口的焊料掩模，使得焊盘的一部分和芯层的每个预定部分的一部分经由开口露出， 以允许导电元件结合到焊盘的暴露部分和焊料掩模的开口中的芯层的预定部分的暴露部分。

公开(公告)号：US20050248885A1

公开(公告)日：2005-11-10

申请号：US11123181

申请日：2005-05-06

Applicant: Yasuhito Funada ,  Tetsuya Ohsawa

Inventor： Yasuhito Funada ,  Tetsuya Ohsawa

IPC: G11B5/60 ,  G11B5/48 ,  G11B21/21 ,  H05K1/00 ,  H05K1/05 ,  H05K3/28

CPC classification number: H05K1/028 ,  G11B5/484 ,  H05K1/056 ,  H05K3/28 ,  H05K2201/0969 ,  H05K2201/0989

Abstract: A suspension board with circuit that can allow precise adjustment of floatation (floatation angle) of even a small-sized slider to a magnetic disc even when the outrigger portions are reduced in rigidity. A gimbal portion 6 of the suspension board with circuit 1 is formed by a tongue portion 10 for mounting a magnetic head thereon, and outrigger portions 11 provided at both sides of the tongue portion 10, and an opening 12 is formed in the insulating cover layer 5 so that the conductor layer 4 can be exposed therefrom in the outrigger portions 11. This can allow reduction in rigidity of the outrigger portions 11, and as such can allow precise adjustment of floatation (floatation angle) of the slider to the magnetic disc even when a small-sized slider is mounted on the gimbal portion.

Abstract translation: 具有电路的悬挂板，即使当外伸支架部分的刚度降低时，也能够将即使小尺寸滑块的浮动（浮动角）精确地调整到磁盘。 具有电路1的悬挂板的万向节部6由用于在其上安装磁头的舌部10形成，并且设置在舌部10的两侧的外伸支架部分11和开口12形成在绝缘覆盖层 5，使得导体层4可以在外伸支架部分11中暴露出来。这可以允许外伸支架部分11的刚性降低，并且因此可以允许精确地调节滑块对磁盘的浮动（浮动角度） 当小型滑块安装在万向节部分上时。

公开(公告)号：US20050247761A1

公开(公告)日：2005-11-10

申请号：US10838897

申请日：2004-05-04

Applicant: Patricia Albanese ,  John Osenbach ,  Thomas Shilling

Inventor： Patricia Albanese ,  John Osenbach ,  Thomas Shilling

IPC: B23K1/00 ,  H05K3/26 ,  H05K3/34 ,  B23K31/00

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L2224/16225 ,  H05K3/26 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10689 ,  H05K2201/10727

Abstract: The specification describes a surface mount method for the manufacture of high device density circuit boards. The stand-off space of the components on the board can be enlarged significantly by selectively omitting, or selectively removing, the soldermask underneath the component package. This improves access of the cleaning fluid to the underside of the component during the cleaning operation.

Abstract translation: 该说明书描述了用于制造高器件密度电路板的表面贴装方法。 通过选择性地省略或选择性地去除组件封装下方的焊接掩模，可以显着增大板上部件的间隔空间。 这在清洁操作期间改善了清洁流体到组件的下侧的访问。

公开(公告)号：US06930255B2

公开(公告)日：2005-08-16

申请号：US10351501

申请日：2003-01-27

Applicant: Yoshinori Wakihara ,  Kazuhito Yamada

Inventor： Yoshinori Wakihara ,  Kazuhito Yamada

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K3/38 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/108 ,  H05K1/0269 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4661 ,  H05K2201/0989 ,  H05K2201/09918 ,  H05K2203/0307 ,  H05K2203/072 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T156/1056 ,  Y10T428/24917

Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.

Abstract translation: 印刷电路板是通过在基板的导体电路上层叠层间绝缘层而形成的，其中导体电路由无电解电镀膜和电解电镀膜构成，并且在至少一部分上形成有粗糙层 导体电路的表面。

公开(公告)号：US20050167815A1

公开(公告)日：2005-08-04

申请号：US11036111

申请日：2005-01-14

Applicant: Kenny Chang ,  Chi-Hsing Hsu

Inventor： Kenny Chang ,  Chi-Hsing Hsu

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16 ,  H05K1/11 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L23/49894 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/111 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/062 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/10636 ,  H05K2203/048 ,  Y02P70/611 ,  Y02P70/613 ,  Y10S257/923 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit carrier and a package structure thereof are provided. The circuit carrier comprises a substrate having a surface, a plurality of passive component electrode pads or a plurality of passive component electrode planes on the surface of the substrate for electrically connecting a passive component corresponding to the plurality of passive component electrode pads, and a solder mask layer covering the surface of the substrate and including at least a solder mask opening, that entirely exposing the passive component electrode pads or a portion of the surface of each the passive component electrode plane corresponding to the passive component. Because there is no solder mask layer between the bottom of the passive component and the substrate, the gap between the passive component and the substrate will become wider. Hence, remaining flux can be entirely removed in order to increase the yield rate of the subsequent high temperature process.

Abstract translation: 提供电路载体及其封装结构。 电路载体包括在基板的表面上具有表面的基板，多个无源部件电极焊盘或多个无源部件电极平面，用于电连接对应于多个无源部件电极焊盘的无源部件，以及焊料 掩模层覆盖基板的表面并且至少包括焊接掩模开口，其完全暴露无源部件电极焊盘或与被动部件对应的每个无源部件电极平面的表面的一部分。 由于在无源部件的底部和基板之间没有焊接掩模层，所以无源部件和基板之间的间隙将变宽。 因此，为了提高随后的高温过程的产率，可以完全除去剩余的通量。

公开(公告)号：US20050167804A1

公开(公告)日：2005-08-04

申请号：US11044836

申请日：2005-01-28

Applicant: Yung Pan ,  Chia Chen

Inventor： Yung Pan ,  Chia Chen

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H01L21/44 ,  H01L23/02

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/099 ,  H01L2924/00014

Abstract: A substrate for packaging a semiconductor chip is disclosed. The substrate includes a dielectric layer, a plurality of conductive circuits and bonding pads formed on the dielectric layer, a metal thin deposition layer formed on the conductive circuits and the bonding pads, and a solder mask formed on the dielectric layer and the conductive circuits. The first ends of the bonding pads extend from the conductive circuits. The metal thin deposition layer has at least a portion to protrude out of the conductive circuits and the bonding pads such that the protruding portion of the metal thin deposition layer is not supported by the conductive circuits or the bonding pads. The bonding pads are exposed from the solder mask except that the second end of each bonding pad is covered by the solder mask in the manner that the protruding portion of the metal thin deposition layer is embedded in the solder mask. The present invention further provides a method for manufacturing a substrate.

Abstract translation: 公开了一种用于封装半导体芯片的基板。 基板包括介电层，形成在电介质层上的多个导电电路和接合焊盘，形成在导电电路和接合焊盘上的金属薄沉积层，以及形成在电介质层和导电电路上的焊接掩模。 接合焊盘的第一端从导电电路延伸。 金属薄沉积层至少有一部分从导电电路和接合焊盘突出出来，使得金属薄沉积层的突出部分不被导电电路或接合焊盘支撑。 接合焊盘从焊料掩模露出，除了金属薄沉积层的突出部分嵌入焊料掩模中的方式，每个接合焊盘的第二端被焊料掩模覆盖。 本发明还提供一种制造基板的方法。